test/CodeGen/AArch64/GlobalISel/regbankselect-unmerge-vec.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
---
name:            unmerge
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $q0

    ; Ensure that the dest regs have FPR since we're unmerging from a vector
    ; CHECK-LABEL: name: unmerge
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s64>) = COPY $q0
    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
    ; CHECK: $x0 = COPY [[UV]](s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(<2 x s64>)
    $x0 = COPY %1(s64)
    RET_ReallyLR implicit $x0

...
---
name:            unmerge_s128
alignment:       4
legalized:       true
tracksRegLiveness: true
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $q0

    ; s128 should be treated as an FPR/vector because it can't live on GPR bank.
    ; CHECK-LABEL: name: unmerge_s128
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(s128) = COPY $q0
    ; CHECK: [[UV:%[0-9]+]]:fpr(s64), [[UV1:%[0-9]+]]:fpr(s64) = G_UNMERGE_VALUES [[COPY]](s128)
    ; CHECK: $x0 = COPY [[UV]](s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(s128) = COPY $q0
    %1:_(s64), %2:_(s64) = G_UNMERGE_VALUES %0(s128)
    $x0 = COPY %1(s64)
    RET_ReallyLR implicit $x0

...