test/CodeGen/AArch64/GlobalISel/regbankselect-reductions.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=regbankselect -global-isel-abort=1 %s -o - | FileCheck %s

---
name:            fadd_v2s32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $d0

    ; CHECK-LABEL: name: fadd_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<2 x s32>) = COPY $d0
    ; CHECK: [[VECREDUCE_FADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_FADD [[COPY]](<2 x s32>)
    ; CHECK: $w0 = COPY [[VECREDUCE_FADD]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(s32) = G_VECREDUCE_FADD %0(<2 x s32>)
    $w0 = COPY %1(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_v4s32
legalized:       true
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $q0

    ; CHECK-LABEL: name: add_v4s32
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:fpr(<4 x s32>) = COPY $q0
    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:fpr(s32) = G_VECREDUCE_ADD [[COPY]](<4 x s32>)
    ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(s32) = G_VECREDUCE_ADD %0(<4 x s32>)
    $w0 = COPY %1(s32)
    RET_ReallyLR implicit $w0

...