test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel %s -o - | FileCheck %s
---
name:            test_loop_phi_fpr_to_gpr
alignment:       4
legalized:       true
regBankSelected: true
selected:        false
failedISel:      false
tracksRegLiveness: true
liveins:         []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
  ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
  ; CHECK:   [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
  ; CHECK:   STRHHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
  ; CHECK:   B %bb.2
  bb.0:
    successors: %bb.1(0x80000000)

    %0:gpr(s1) = G_IMPLICIT_DEF
    %4:gpr(p0) = G_IMPLICIT_DEF
    %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000

  bb.1:
    successors: %bb.2(0x80000000)

    %6:gpr(s32) = G_IMPLICIT_DEF
    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
    %1:gpr(s16) = G_TRUNC %7(s32)

  bb.2:
    successors: %bb.2(0x80000000)

    %3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
    %5:fpr(s16) = G_FPTRUNC %8(s32)
    G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
    G_BR %bb.2

...
---
name:            test_loop_phi_gpr_to_fpr
alignment:       4
legalized:       true
regBankSelected: true
selected:        false
failedISel:      false
tracksRegLiveness: true
liveins:         []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
  ; CHECK:   [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
  ; CHECK:   [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
  ; CHECK:   [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
  ; CHECK: bb.2:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
  ; CHECK:   [[FCVTHSr:%[0-9]+]]:fpr16 = FCVTHSr [[COPY]]
  ; CHECK:   STRHui [[PHI]], [[DEF1]], 0 :: (store 2 into `half* undef`)
  ; CHECK:   B %bb.2
  bb.0:
    successors: %bb.1(0x80000000)

    %0:gpr(s1) = G_IMPLICIT_DEF
    %4:gpr(p0) = G_IMPLICIT_DEF
    %8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000

  bb.1:
    successors: %bb.2(0x80000000)

    %6:gpr(s32) = G_IMPLICIT_DEF
    %7:gpr(s32) = G_SELECT %0(s1), %6, %6
    %1:gpr(s16) = G_TRUNC %7(s32)

  bb.2:
    successors: %bb.2(0x80000000)

    %3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
    %5:fpr(s16) = G_FPTRUNC %8(s32)
    G_STORE %3(s16), %4(p0) :: (store 2 into `half* undef`)
    G_BR %bb.2

...