test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-trivial-arith.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

name:            right_ident_sub
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x - 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_sub
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_SUB %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            right_ident_add
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x + 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_add
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_ADD %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            mul_0
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x * 0) -> 0
    ;
    ; CHECK-LABEL: name: mul_0
    ; CHECK: liveins: $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: $w0 = COPY %cst(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_MUL %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...

# FIXME: Probably should be able to replace this.
---
name:            mul_0_cant_replace
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x * 0) -> 0
    ;
    ; CHECK-LABEL: name: mul_0_cant_replace
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: %op:gpr(s32) = G_MUL %x, %cst
    ; CHECK: $w0 = COPY %op(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:gpr(s32) = G_MUL %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...

---
name:            sdiv_0
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (0 / x) -> 0
    ;
    ; CHECK-LABEL: name: sdiv_0
    ; CHECK: liveins: $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: $w0 = COPY %cst(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_SDIV %cst, %x
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            udiv_0
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (0 / x) -> 0
    ;
    ; CHECK-LABEL: name: udiv_0
    ; CHECK: liveins: $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: $w0 = COPY %cst(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_UDIV %cst, %x
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            srem_0
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (0 % x) -> 0
    ;
    ; CHECK-LABEL: name: srem_0
    ; CHECK: liveins: $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: $w0 = COPY %cst(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_SREM %cst, %x
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            urem_0
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (0 % x) -> 0
    ;
    ; CHECK-LABEL: name: urem_0
    ; CHECK: liveins: $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 0
    ; CHECK: $w0 = COPY %cst(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_UREM %cst, %x
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...

---
name:            right_ident_or
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x || 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_or
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_OR %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            right_ident_xor
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x | 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_xor
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_XOR %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            right_ident_shl
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x << 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_shl
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_SHL %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            right_ident_ashr
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x ashr 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_ashr
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_ASHR %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            right_ident_lshr
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Fold (x lshr 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_lshr
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: $w0 = COPY %x(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 0
    %op:_(s32) = G_LSHR %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            dont_fold_sub
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $w0
    ; Not an identity, no folding.
    ;
    ; CHECK-LABEL: name: dont_fold_sub
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %cst:_(s32) = G_CONSTANT i32 1
    ; CHECK: %op:_(s32) = G_SUB %x, %cst
    ; CHECK: $w0 = COPY %op(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %cst:_(s32) = G_CONSTANT i32 1
    %op:_(s32) = G_SUB %x(s32), %cst
    $w0 = COPY %op(s32)
    RET_ReallyLR implicit $w0

...
---
name:            look_through_zext
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: look_through_zext
    ; CHECK: liveins: $x0
    ; CHECK: %zero:_(s8) = G_CONSTANT i8 0
    ; CHECK: %zext_zero:_(s64) = G_ZEXT %zero(s8)
    ; CHECK: $x0 = COPY %zext_zero(s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %zero:_(s8) = G_CONSTANT i8 0
    %zext_zero:_(s64) = G_ZEXT %zero(s8)
    %c:_(s64) = G_CONSTANT i64 72340172838076673
    %mul:_(s64) = G_MUL %c, %zext_zero
    $x0 = COPY %mul(s64)
    RET_ReallyLR implicit $x0
...
---
name:            right_ident_ptr_add
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $x0
    ; Fold (x + 0) -> x
    ;
    ; CHECK-LABEL: name: right_ident_ptr_add
    ; CHECK: liveins: $x0
    ; CHECK: %x:_(p0) = COPY $x0
    ; CHECK: $x0 = COPY %x(p0)
    ; CHECK: RET_ReallyLR implicit $x0
    %x:_(p0) = COPY $x0
    %cst:_(s64) = G_CONSTANT i64 0
    %op:_(p0) = G_PTR_ADD %x(p0), %cst
    $x0 = COPY %op(p0)
    RET_ReallyLR implicit $x0