test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-ashr-shl-to-sext-inreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name:            ashr_shl_to_sext_inreg
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: ashr_shl_to_sext_inreg
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s16) = G_SEXT_INREG [[TRUNC]], 8
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SEXT_INREG]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %1:_(s32) = COPY $w0
    %0:_(s16) = G_TRUNC %1(s32)
    %2:_(s16) = G_CONSTANT i16 8
    %3:_(s16) = G_SHL %0, %2(s16)
    %4:_(s16) = exact G_ASHR %3, %2(s16)
    %5:_(s32) = G_ANYEXT %4(s16)
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            different_shift_amts
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$w0' }
body:             |
  bb.1:
    liveins: $w0

    ; CHECK-LABEL: name: different_shift_amts
    ; CHECK: liveins: $w0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
    ; CHECK: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
    ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
    ; CHECK: [[ASHR:%[0-9]+]]:_(s16) = exact G_ASHR [[SHL]], [[C1]](s16)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %1:_(s32) = COPY $w0
    %0:_(s16) = G_TRUNC %1(s32)
    %2:_(s16) = G_CONSTANT i16 12
    %4:_(s16) = G_CONSTANT i16 8
    %3:_(s16) = G_SHL %0, %2(s16)
    %5:_(s16) = exact G_ASHR %3, %4(s16)
    %6:_(s32) = G_ANYEXT %5(s16)
    $w0 = COPY %6(s32)
    RET_ReallyLR implicit $w0

...
---
name:            ashr_shl_to_sext_inreg_vector
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$d0' }
body:             |
  bb.1:
    liveins: $d0
    ; Currently don't support this for vectors just yet, this will need updating
    ; when we do.
    ; CHECK-LABEL: name: ashr_shl_to_sext_inreg_vector
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
    ; CHECK: [[SHL:%[0-9]+]]:_(<4 x s16>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<4 x s16>)
    ; CHECK: [[ASHR:%[0-9]+]]:_(<4 x s16>) = exact G_ASHR [[SHL]], [[BUILD_VECTOR]](<4 x s16>)
    ; CHECK: $d0 = COPY [[ASHR]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %2:_(s16) = G_CONSTANT i16 8
    %1:_(<4 x s16>) = G_BUILD_VECTOR %2(s16), %2(s16), %2(s16), %2(s16)
    %3:_(<4 x s16>) = G_SHL %0, %1(<4 x s16>)
    %4:_(<4 x s16>) = exact G_ASHR %3, %1(<4 x s16>)
    $d0 = COPY %4(<4 x s16>)
    RET_ReallyLR implicit $d0
...