test/CodeGen/AArch64/GlobalISel/legalize-ctlz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name:            test_v8s8
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v8s8
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<8 x s8>) = G_CTLZ [[COPY]](<8 x s8>)
    ; CHECK: $d0 = COPY [[CTLZ]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = G_CTLZ %0(<8 x s8>)
    $d0 = COPY %1(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4s16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v4s16
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<4 x s16>) = G_CTLZ [[COPY]](<4 x s16>)
    ; CHECK: $d0 = COPY [[CTLZ]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = G_CTLZ %0(<4 x s16>)
    $d0 = COPY %1(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_v2s32
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<2 x s32>) = G_CTLZ [[COPY]](<2 x s32>)
    ; CHECK: $d0 = COPY [[CTLZ]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = G_CTLZ %0(<2 x s32>)
    $d0 = COPY %1(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_s64
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_s64
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY1]](s64)
    ; CHECK: $d0 = COPY [[CTLZ]](s64)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(s64) = COPY $d0
    %2:_(s64) = COPY %0(s64)
    %1:_(s64) = G_CTLZ %2(s64)
    $d0 = COPY %1(s64)
    RET_ReallyLR implicit $d0

...
---
name:            test_s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $s0
    ; CHECK-LABEL: name: test_s32
    ; CHECK: liveins: $s0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
    ; CHECK: $s0 = COPY [[CTLZ]](s32)
    ; CHECK: RET_ReallyLR implicit $s0
    %0:_(s32) = COPY $s0
    %2:_(s32) = COPY %0(s32)
    %1:_(s32) = G_CTLZ %2(s32)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            test_v16s8
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v16s8
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<16 x s8>) = G_CTLZ [[COPY]](<16 x s8>)
    ; CHECK: $q0 = COPY [[CTLZ]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = G_CTLZ %0(<16 x s8>)
    $q0 = COPY %1(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8s16
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v8s16
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<8 x s16>) = G_CTLZ [[COPY]](<8 x s16>)
    ; CHECK: $q0 = COPY [[CTLZ]](<8 x s16>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = G_CTLZ %0(<8 x s16>)
    $q0 = COPY %1(<8 x s16>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v4s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: test_v4s32
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[CTLZ:%[0-9]+]]:_(<4 x s32>) = G_CTLZ [[COPY]](<4 x s32>)
    ; CHECK: $q0 = COPY [[CTLZ]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = G_CTLZ %0(<4 x s32>)
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0

...

# The ZERO_UNDEF variants just lower into the vanilla ones.
---
name:            test_s32_zeroundef
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $s0
    ; CHECK-LABEL: name: test_s32_zeroundef
    ; CHECK: liveins: $s0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY1]](s32)
    ; CHECK: $s0 = COPY [[CTLZ]](s32)
    ; CHECK: RET_ReallyLR implicit $s0
    %0:_(s32) = COPY $s0
    %2:_(s32) = COPY %0(s32)
    %1:_(s32) = G_CTLZ_ZERO_UNDEF %2(s32)
    $s0 = COPY %1(s32)
    RET_ReallyLR implicit $s0

...
---
name:            test_s64_zeroundef
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $d0

    ; CHECK-LABEL: name: test_s64_zeroundef
    ; CHECK: liveins: $d0
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[COPY1]](s64)
    ; CHECK: $d0 = COPY [[CTLZ]](s64)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(s64) = COPY $d0
    %2:_(s64) = COPY %0(s64)
    %1:_(s64) = G_CTLZ_ZERO_UNDEF %2(s64)
    $d0 = COPY %1(s64)
    RET_ReallyLR implicit $d0

...