test/CodeGen/AArch64/GlobalISel/form-bitfield-extract-from-sextinreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

# Check that we can fold a G_SEXT_INREG fed by a G_ASHR/G_LSHR into a G_SBFX.

...
---
name:            sextinreg_ashr_to_sbfx
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: sextinreg_ashr_to_sbfx
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
    ; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]](s32), [[C1]]
    ; CHECK: $w0 = COPY %sext_inreg(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %lsb:_(s32) = G_CONSTANT i32 5
    %shift:_(s32) = G_ASHR %x, %lsb
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
    $w0 = COPY %sext_inreg
    RET_ReallyLR implicit $w0

...
---
name:            sextinreg_lshr_to_sbfx
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: sextinreg_lshr_to_sbfx
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
    ; CHECK: %sext_inreg:_(s32) = G_SBFX %x, [[C]](s32), [[C1]]
    ; CHECK: $w0 = COPY %sext_inreg(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %lsb:_(s32) = G_CONSTANT i32 5
    %shift:_(s32) = G_LSHR %x, %lsb
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
    $w0 = COPY %sext_inreg
    RET_ReallyLR implicit $w0


...
---
name:            dont_apply_no_constant
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0
    ; AArch64 needs a constant on the shift for this combine.

    ; CHECK-LABEL: name: dont_apply_no_constant
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %y:_(s32) = COPY $w0
    ; CHECK: %shift:_(s32) = G_LSHR %x, %y(s32)
    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
    ; CHECK: $w0 = COPY %sext_inreg(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %y:_(s32) = COPY $w0
    %shift:_(s32) = G_LSHR %x, %y
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 10
    $w0 = COPY %sext_inreg
    RET_ReallyLR implicit $w0

...
---
name:            dont_apply_shift_imm_too_large
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0

    ; LSB must be in 0-31.

    ; CHECK-LABEL: name: dont_apply_shift_imm_too_large
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 32
    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    ; CHECK: $w0 = COPY %sext_inreg(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %lsb:_(s32) = G_CONSTANT i32 32
    %shift:_(s32) = G_ASHR %x, %lsb
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    $w0 = COPY %sext_inreg
    RET_ReallyLR implicit $w0

...
---
name:            dont_apply_negative_shift_imm
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0

    ; LSB must be in 0-31.

    ; CHECK-LABEL: name: dont_apply_negative_shift_imm
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 -1
    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    ; CHECK: $w0 = COPY %sext_inreg(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %lsb:_(s32) = G_CONSTANT i32 -1
    %shift:_(s32) = G_ASHR %x, %lsb
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    $w0 = COPY %sext_inreg
    RET_ReallyLR implicit $w0

...
---
name:            dont_apply_more_than_one_use
tracksRegLiveness: true
legalized: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: dont_apply_more_than_one_use
    ; CHECK: liveins: $w0
    ; CHECK: %x:_(s32) = COPY $w0
    ; CHECK: %lsb:_(s32) = G_CONSTANT i32 1
    ; CHECK: %shift:_(s32) = G_ASHR %x, %lsb(s32)
    ; CHECK: %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    ; CHECK: %mul:_(s32) = G_MUL %shift, %sext_inreg
    ; CHECK: $w0 = COPY %mul(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %x:_(s32) = COPY $w0
    %lsb:_(s32) = G_CONSTANT i32 1
    %shift:_(s32) = G_ASHR %x, %lsb
    %sext_inreg:_(s32) = G_SEXT_INREG %shift, 1
    %mul:_(s32) = G_MUL %shift, %sext_inreg
    $w0 = COPY %mul
    RET_ReallyLR implicit $w0