test/CodeGen/AArch64/GlobalISel/combine-mul-to-shl.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
...
---
name:            mul_to_shl
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: mul_to_shl
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; CHECK: $x0 = COPY [[SHL]](s64)
    ; CHECK: RET_ReallyLR implicit-def $x0
    %0:_(s64) = COPY $x0
    %1:_(s64) = G_CONSTANT i64 4
    %2:_(s64) = G_MUL %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit-def $x0
...
---
name:            mul_to_shl_16
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: mul_to_shl_16
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
    ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
    ; CHECK: $x0 = COPY [[SHL]](s64)
    ; CHECK: RET_ReallyLR implicit-def $x0
    %0:_(s64) = COPY $x0
    %1:_(s64) = G_CONSTANT i64 16
    %2:_(s64) = G_MUL %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit-def $x0
...
---
name:            mul_to_shl_vector_16
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $q0
    ; Currently not implemented.
    ; CHECK-LABEL: name: mul_to_shl_vector_16
    ; CHECK: liveins: $q0
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
    ; CHECK: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[COPY]], [[BUILD_VECTOR]]
    ; CHECK: $q0 = COPY [[MUL]](<4 x s32>)
    ; CHECK: RET_ReallyLR implicit-def $q0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(s32) = G_CONSTANT i32 16
    %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
    %3:_(<4 x s32>) = G_MUL %0, %2(<4 x s32>)
    $q0 = COPY %3(<4 x s32>)
    RET_ReallyLR implicit-def $q0
...
---
name:            mul_to_shl_non_pow2
alignment:       4
tracksRegLiveness: true
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: mul_to_shl_non_pow2
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 10
    ; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[C]]
    ; CHECK: $x0 = COPY [[MUL]](s64)
    ; CHECK: RET_ReallyLR implicit-def $x0
    %0:_(s64) = COPY $x0
    %1:_(s64) = G_CONSTANT i64 10
    %2:_(s64) = G_MUL %0, %1(s64)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit-def $x0
...