test/CodeGen/NVPTX/f32-lg2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mcpu=sm_20 -mattr=+ptx32 | FileCheck --check-prefixes=CHECK %s
; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -mattr=+ptx32 | %ptxas-verify %}
target triple = "nvptx64-nvidia-cuda"

declare float @llvm.nvvm.lg2.approx.f(float)
declare float @llvm.nvvm.lg2.approx.ftz.f(float)

; CHECK-LABEL: lg2_float
define float @lg2_float(float %0) {
; CHECK-LABEL: lg2_float(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [lg2_float_param_0];
; CHECK-NEXT:    lg2.approx.f32 %r2, %r1;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r2;
; CHECK-NEXT:    ret;
  %res = call float @llvm.nvvm.lg2.approx.f(float %0)
  ret float %res
}

; CHECK-LABEL: lg2_float_ftz
define float @lg2_float_ftz(float %0) {
; CHECK-LABEL: lg2_float_ftz(
; CHECK:       {
; CHECK-NEXT:    .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.b32 %r1, [lg2_float_ftz_param_0];
; CHECK-NEXT:    lg2.approx.ftz.f32 %r2, %r1;
; CHECK-NEXT:    st.param.b32 [func_retval0], %r2;
; CHECK-NEXT:    ret;
  %res = call float @llvm.nvvm.lg2.approx.ftz.f(float %0)
  ret float %res
}