test/Transforms/SROA/slice-order-independence.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"

declare void @llvm.memcpy.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind

; Check that the chosen type for a split is independent from the order of
; slices even in case of types that are skipped because their width is not a
; byte width multiple
define void @skipped_inttype_first(ptr) {
; CHECK-LABEL: @skipped_inttype_first(
; CHECK-NEXT:    [[ARG_SROA_0:%.*]] = alloca ptr, align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[TMP0:%.*]], align 8
; CHECK-NEXT:    store ptr [[ARG_SROA_0_0_COPYLOAD]], ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    [[ARG_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8
; CHECK-NEXT:    [[ARG_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[ARG_SROA_3_0__SROA_IDX]], align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_B0:%.*]] = load i63, ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_B1:%.*]] = load ptr, ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    ret void
;
  %arg = alloca { ptr, i32 }, align 8
  call void @llvm.memcpy.p0.p0.i32(ptr align 8 %arg, ptr align 8 %0, i32 16, i1 false)
  %b = getelementptr inbounds { ptr, i32 }, ptr %arg, i64 0, i32 0
  %b0 = load i63, ptr %b
  %b1 = load ptr, ptr %b
  ret void
}

define void @skipped_inttype_last(ptr) {
; CHECK-LABEL: @skipped_inttype_last(
; CHECK-NEXT:    [[ARG_SROA_0:%.*]] = alloca ptr, align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_COPYLOAD:%.*]] = load ptr, ptr [[TMP0:%.*]], align 8
; CHECK-NEXT:    store ptr [[ARG_SROA_0_0_COPYLOAD]], ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    [[ARG_SROA_3_0__SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8
; CHECK-NEXT:    [[ARG_SROA_3_0_COPYLOAD:%.*]] = load i64, ptr [[ARG_SROA_3_0__SROA_IDX]], align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_B1:%.*]] = load ptr, ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    [[ARG_SROA_0_0_ARG_SROA_0_0_B0:%.*]] = load i63, ptr [[ARG_SROA_0]], align 8
; CHECK-NEXT:    ret void
;
  %arg = alloca { ptr, i32 }, align 8
  call void @llvm.memcpy.p0.p0.i32(ptr align 8 %arg, ptr align 8 %0, i32 16, i1 false)
  %b = getelementptr inbounds { ptr, i32 }, ptr %arg, i64 0, i32 0
  %b1 = load ptr, ptr %b
  %b0 = load i63, ptr %b
  ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-MODIFY-CFG: {{.*}}
; CHECK-PRESERVE-CFG: {{.*}}