test/Transforms/OpenMP/custom_state_machines_pre_lto.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs
; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU1
; RUN: opt --mtriple=nvptx64--         -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=NVPTX1
; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=AMDGPU2
; RUN: opt --mtriple=amdgcn-amd-amdhsa --data-layout=A5 -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=AMDGPU3
; RUN: opt --mtriple=nvptx64--         -openmp-opt-disable-state-machine-rewrite -S -passes=openmp-opt < %s | FileCheck %s --check-prefix=NVPTX2
; RUN: opt --mtriple=nvptx64--         -S -passes=openmp-opt-postlink < %s | FileCheck %s --check-prefix=NVPTX3

;; void p0(void);
;; void p1(void);
;; int unknown(void);
;; void unknown_pure(void) __attribute__((pure));
;; void unknown_no_openmp(void) __attribute__((assume("omp_no_openmp")));
;;
;; int G;
;; void no_parallel_region_in_here(void) {
;; #pragma omp single
;;   G = 0;
;; }
;;
;; void no_state_machine_needed() {
;; #pragma omp target teams
;;   {
;;     no_parallel_region_in_here();
;;     unknown_no_openmp();
;;   }
;; }
;;
;; void simple_state_machine() {
;; #pragma omp target teams
;;   {
;;     unknown_no_openmp();
;; #pragma omp parallel
;;     { p0(); }
;;     no_parallel_region_in_here();
;; #pragma omp parallel
;;     { p1(); }
;;   }
;; }
;;
;; void simple_state_machine_interprocedural_after(void);
;; void simple_state_machine_interprocedural_before(void) {
;; #pragma omp parallel
;;   { p0(); }
;; }
;; void simple_state_machine_interprocedural() {
;; #pragma omp target teams
;;   {
;;     unknown_no_openmp();
;;     simple_state_machine_interprocedural_before();
;;     no_parallel_region_in_here();
;; #pragma omp parallel
;;     { p1(); }
;;     simple_state_machine_interprocedural_after();
;;   }
;; }
;; void simple_state_machine_interprocedural_after(void) {
;; #pragma omp parallel
;;   { p0(); }
;; }
;;
;; void simple_state_machine_with_fallback() {
;; #pragma omp target teams
;;   {
;; #pragma omp parallel
;;     { p0(); }
;;     unknown();
;; #pragma omp parallel
;;     { p1(); }
;;   }
;; }
;;
;; void simple_state_machine_no_openmp_attr() {
;; #pragma omp target teams
;;   {
;; #pragma omp parallel
;;     { p0(); }
;;     unknown_no_openmp();
;; #pragma omp parallel
;;     { p1(); }
;;   }
;; }
;;
;; void simple_state_machine_pure() {
;; #pragma omp target teams
;;   {
;;     unknown_no_openmp();
;; #pragma omp parallel
;;     { p0(); }
;;     unknown_pure();
;; #pragma omp parallel
;;     { p1(); }
;;   }
;; }
;;
;; int omp_get_thread_num();
;; void simple_state_machine_interprocedural_nested_recursive_after(int);
;; void simple_state_machine_interprocedural_nested_recursive_after_after(void);
;; void simple_state_machine_interprocedural_nested_recursive() {
;; #pragma omp target teams
;;   {
;;     simple_state_machine_interprocedural_nested_recursive_after(
;;         omp_get_thread_num());
;;   }
;; }
;;
;; void simple_state_machine_interprocedural_nested_recursive_after(int a) {
;;   if (a == 0)
;;     return;
;;   simple_state_machine_interprocedural_nested_recursive_after(a - 1);
;;   simple_state_machine_interprocedural_nested_recursive_after_after();
;; }
;; void simple_state_machine_interprocedural_nested_recursive_after_after(void) {
;; #pragma omp parallel
;;   { p0(); }
;; }
;;
;; __attribute__((weak)) void weak_callee_empty(void) {}
;; void no_state_machine_weak_callee() {
;; #pragma omp target teams
;;   { weak_callee_empty(); }
;; }

%struct.ident_t = type { i32, i32, i32, i32, ptr }
%struct.KernelEnvironmentTy = type { %struct.ConfigurationEnvironmentTy, ptr, ptr }
%struct.ConfigurationEnvironmentTy = type { i8, i8, i8 }

@0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1
@1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 0, ptr @0 }, align 8
@2 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 2, i32 0, ptr @0 }, align 8
@G = external global i32, align 4
@3 = private unnamed_addr constant %struct.ident_t { i32 0, i32 322, i32 2, i32 0, ptr @0 }, align 8
@__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }
@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment = local_unnamed_addr constant %struct.KernelEnvironmentTy { %struct.ConfigurationEnvironmentTy { i8 1, i8 0, i8 1 }, ptr @1, ptr null }

define weak void @__omp_offloading_14_a36502b_no_state_machine_needed_l14() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

; Make it a declaration so we will *not* apply custom state machine rewriting and wait for LTO.
declare i32 @__kmpc_target_init(ptr);

define internal void @__omp_outlined__(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @no_parallel_region_in_here() #7
  call void @unknown_no_openmp() #8
  ret void
}

define hidden void @no_parallel_region_in_here() #1 {
entry:
  %0 = call i32 @__kmpc_global_thread_num(ptr @2)
  %1 = call i32 @__kmpc_single(ptr @2, i32 %0)
  %2 = icmp ne i32 %1, 0
  br i1 %2, label %omp_if.then, label %omp_if.end

omp_if.then:                                      ; preds = %entry
  store i32 0, ptr @G, align 4
  call void @__kmpc_end_single(ptr @2, i32 %0)
  br label %omp_if.end

omp_if.end:                                       ; preds = %omp_if.then, %entry
  call void @__kmpc_barrier(ptr @3, i32 %0)
  ret void
}

declare void @unknown_no_openmp() #2

declare i32 @__kmpc_global_thread_num(ptr) #3

declare void @__kmpc_target_deinit()

define weak void @__omp_offloading_14_a36502b_simple_state_machine_l22() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__1(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__1(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %captured_vars_addrs1 = alloca [0 x ptr], align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @unknown_no_openmp() #8
  %0 = load ptr, ptr %.global_tid..addr, align 8
  %1 = load i32, ptr %0, align 4
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr %captured_vars_addrs, i64 0)
  call void @no_parallel_region_in_here() #7
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr %captured_vars_addrs1, i64 0)
  ret void
}

define internal void @__omp_outlined__2(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

declare void @p0() #4

define internal void @__omp_outlined__2_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__2(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

declare void @__kmpc_get_shared_variables(ptr)

declare void @__kmpc_parallel_51(ptr, i32, i32, i32, i32, ptr, ptr, ptr, i64)

define internal void @__omp_outlined__3(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p1() #7
  ret void
}

declare void @p1() #4

define internal void @__omp_outlined__3_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__3(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define weak void @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__4(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__4(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  %captured_vars_addrs = alloca [0 x ptr], align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @unknown_no_openmp() #8
  call void @simple_state_machine_interprocedural_before() #7
  call void @no_parallel_region_in_here() #7
  %0 = load ptr, ptr %.global_tid..addr, align 8
  %1 = load i32, ptr %0, align 4
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr %captured_vars_addrs, i64 0)
  call void @simple_state_machine_interprocedural_after() #7
  ret void
}

define hidden void @simple_state_machine_interprocedural_before() #1 {
entry:
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %0 = call i32 @__kmpc_global_thread_num(ptr @2)
  call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr %captured_vars_addrs, i64 0)
  ret void
}

define internal void @__omp_outlined__5(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p1() #7
  ret void
}

define internal void @__omp_outlined__5_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__5(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define hidden void @simple_state_machine_interprocedural_after() #1 {
entry:
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %0 = call i32 @__kmpc_global_thread_num(ptr @2)
  call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr %captured_vars_addrs, i64 0)
  ret void
}

define weak void @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__6(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__6(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %captured_vars_addrs1 = alloca [0 x ptr], align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  %0 = load ptr, ptr %.global_tid..addr, align 8
  %1 = load i32, ptr %0, align 4
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr %captured_vars_addrs, i64 0)
  %call = call i32 @unknown() #7
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr %captured_vars_addrs1, i64 0)
  ret void
}

define internal void @__omp_outlined__7(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__7_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__7(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

declare i32 @unknown() #4

define internal void @__omp_outlined__8(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p1() #7
  ret void
}

define internal void @__omp_outlined__8_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__8(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define weak void @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__9(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__9(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %captured_vars_addrs1 = alloca [0 x ptr], align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  %0 = load ptr, ptr %.global_tid..addr, align 8
  %1 = load i32, ptr %0, align 4
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr %captured_vars_addrs, i64 0)
  call void @unknown_no_openmp() #8
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr %captured_vars_addrs1, i64 0)
  ret void
}

define internal void @__omp_outlined__10(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__10_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__10(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define internal void @__omp_outlined__11(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p1() #7
  ret void
}

define internal void @__omp_outlined__11_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__11(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define weak void @__omp_offloading_14_a36502b_simple_state_machine_pure_l77() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__12(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__12(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %captured_vars_addrs1 = alloca [0 x ptr], align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @unknown_no_openmp() #8
  %0 = load ptr, ptr %.global_tid..addr, align 8
  %1 = load i32, ptr %0, align 4
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr %captured_vars_addrs, i64 0)
  call void @unknown_pure() #9
  call void @__kmpc_parallel_51(ptr @1, i32 %1, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr %captured_vars_addrs1, i64 0)
  ret void
}

define internal void @__omp_outlined__13(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__13_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__13(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

declare void @unknown_pure() #5

define internal void @__omp_outlined__14(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p1() #7
  ret void
}

define internal void @__omp_outlined__14_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__14(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define weak void @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__15(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__15(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  %call = call i32 @omp_get_thread_num() #7
  call void @simple_state_machine_interprocedural_nested_recursive_after(i32 %call) #7
  ret void
}

define hidden void @simple_state_machine_interprocedural_nested_recursive_after(i32 %a) #1 {
entry:
  %a.addr = alloca i32, align 4
  store i32 %a, ptr %a.addr, align 4
  %0 = load i32, ptr %a.addr, align 4
  %cmp = icmp eq i32 %0, 0
  br i1 %cmp, label %if.then, label %if.end

if.then:                                          ; preds = %entry
  br label %return

if.end:                                           ; preds = %entry
  %1 = load i32, ptr %a.addr, align 4
  %sub = sub nsw i32 %1, 1
  call void @simple_state_machine_interprocedural_nested_recursive_after(i32 %sub) #7
  call void @simple_state_machine_interprocedural_nested_recursive_after_after() #7
  br label %return

return:                                           ; preds = %if.end, %if.then
  ret void
}

declare i32 @omp_get_thread_num(...) #4

define weak void @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112() #0 {
entry:
  %.zero.addr = alloca i32, align 4
  %.threadid_temp. = alloca i32, align 4
  store i32 0, ptr %.zero.addr, align 4
  %0 = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
  %exec_user_code = icmp eq i32 %0, -1
  br i1 %exec_user_code, label %user_code.entry, label %worker.exit

user_code.entry:                                  ; preds = %entry
  %1 = call i32 @__kmpc_global_thread_num(ptr @1)
  store i32 %1, ptr %.threadid_temp., align 4
  call void @__omp_outlined__16(ptr %.threadid_temp., ptr %.zero.addr) #3
  call void @__kmpc_target_deinit()
  ret void

worker.exit:                                      ; preds = %entry
  ret void
}

define internal void @__omp_outlined__16(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @weak_callee_empty() #7
  ret void
}

define weak hidden void @weak_callee_empty() #1 {
entry:
  ret void
}

declare i32 @__kmpc_single(ptr, i32) #6

declare void @__kmpc_end_single(ptr, i32) #6

declare void @__kmpc_barrier(ptr, i32) #6

define internal void @__omp_outlined__17(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__17_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__17(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define internal void @__omp_outlined__18(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__18_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__18(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

define hidden void @simple_state_machine_interprocedural_nested_recursive_after_after() #1 {
entry:
  %captured_vars_addrs = alloca [0 x ptr], align 8
  %0 = call i32 @__kmpc_global_thread_num(ptr @2)
  call void @__kmpc_parallel_51(ptr @2, i32 %0, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr %captured_vars_addrs, i64 0)
  ret void
}

define internal void @__omp_outlined__19(ptr noalias %.global_tid., ptr noalias %.bound_tid.) #0 {
entry:
  %.global_tid..addr = alloca ptr, align 8
  %.bound_tid..addr = alloca ptr, align 8
  store ptr %.global_tid., ptr %.global_tid..addr, align 8
  store ptr %.bound_tid., ptr %.bound_tid..addr, align 8
  call void @p0() #7
  ret void
}

define internal void @__omp_outlined__19_wrapper(i16 zeroext %0, i32 %1) #0 {
entry:
  %.addr = alloca i16, align 2
  %.addr1 = alloca i32, align 4
  %.zero.addr = alloca i32, align 4
  %global_args = alloca ptr, align 8
  store i32 0, ptr %.zero.addr, align 4
  store i16 %0, ptr %.addr, align 2
  store i32 %1, ptr %.addr1, align 4
  call void @__kmpc_get_shared_variables(ptr %global_args)
  call void @__omp_outlined__19(ptr %.addr1, ptr %.zero.addr) #3
  ret void
}

attributes #0 = { convergent noinline norecurse nounwind "kernel" "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
attributes #1 = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
attributes #2 = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
attributes #3 = { nounwind }
attributes #4 = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
attributes #5 = { convergent nounwind readonly willreturn "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
attributes #6 = { convergent nounwind }
attributes #7 = { convergent }
attributes #8 = { convergent "llvm.assume"="omp_no_openmp" }
attributes #9 = { convergent nounwind readonly willreturn }

!omp_offload.info = !{!0, !1, !2, !3, !4, !5, !6, !7}
!nvvm.annotations = !{!8, !9, !10, !11, !12, !13, !14, !15}
!llvm.module.flags = !{!16, !17, !18}

!0 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
!1 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
!2 = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
!3 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
!4 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
!5 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
!6 = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
!7 = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
!8 = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
!9 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
!10 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
!11 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
!12 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
!13 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
!14 = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
!15 = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
!16 = !{i32 1, !"wchar_size", i32 4}
!17 = !{i32 7, !"openmp", i32 50}
!18 = !{i32 7, !"openmp-device", i32 50}
;.
; AMDGPU1: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; AMDGPU1: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU1: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU1: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; AMDGPU1: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; AMDGPU1: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; NVPTX1: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; NVPTX1: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX1: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX1: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; NVPTX1: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; NVPTX1: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; AMDGPU2: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; AMDGPU2: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU2: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU2: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; AMDGPU2: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; AMDGPU2: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; AMDGPU3: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; AMDGPU3: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU3: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU3: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; AMDGPU3: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; AMDGPU3: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; NVPTX2: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; NVPTX2: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX2: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX2: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; NVPTX2: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; NVPTX2: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; NVPTX3: @[[GLOB0:[0-9]+]] = private unnamed_addr constant [23 x i8] c"
; NVPTX3: @[[GLOB1:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 0, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX3: @[[GLOB2:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 2, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX3: @[[G:[a-zA-Z0-9_$"\\.-]+]] = external global i32, align 4
; NVPTX3: @[[GLOB3:[0-9]+]] = private unnamed_addr constant [[STRUCT_IDENT_T:%.*]] { i32 0, i32 322, i32 2, i32 0, ptr @[[GLOB0]] }, align 8
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_NEEDED_L14_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_L22_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_L39_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_WITH_FALLBACK_L55_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_NO_OPENMP_ATTR_L66_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_PURE_L77_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 1, i8 1 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_SIMPLE_STATE_MACHINE_INTERPROCEDURAL_NESTED_RECURSIVE_L92_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 0, i8 1, i8 3 }, ptr @[[GLOB1]], ptr null }
; NVPTX3: @[[__OMP_OFFLOADING_14_A36502B_NO_STATE_MACHINE_WEAK_CALLEE_L112_KERNEL_ENVIRONMENT:[a-zA-Z0-9_$"\\.-]+]] = local_unnamed_addr constant [[STRUCT_KERNELENVIRONMENTTY:%.*]] { [[STRUCT_CONFIGURATIONENVIRONMENTTY:%.*]] { i8 1, i8 0, i8 1 }, ptr @[[GLOB1]], ptr null }
;.
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; AMDGPU1-SAME: () #[[ATTR0:[0-9]+]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; AMDGPU1-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; AMDGPU1-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; AMDGPU1-SAME: () #[[ATTR1:[0-9]+]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU1-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU1-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU1:       omp_if.then:
; AMDGPU1-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU1-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU1-NEXT:    br label [[OMP_IF_END]]
; AMDGPU1:       omp_if.end:
; AMDGPU1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; AMDGPU1-SAME: () #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU1-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU1-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU1:       omp_if.then:
; AMDGPU1-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU1-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU1-NEXT:    br label [[OMP_IF_END]]
; AMDGPU1:       omp_if.end:
; AMDGPU1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__1
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__2
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__3
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__4
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; AMDGPU1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; AMDGPU1-SAME: () #[[ATTR6:[0-9]+]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; AMDGPU1-SAME: () #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__5
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; AMDGPU1-SAME: () #[[ATTR6]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; AMDGPU1-SAME: () #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__6
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__7
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__8
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__9
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__10
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__11
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__12
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__13
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__14
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__15
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; AMDGPU1-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU1:       if.then:
; AMDGPU1-NEXT:    br label [[RETURN:%.*]]
; AMDGPU1:       if.end:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; AMDGPU1-NEXT:    br label [[RETURN]]
; AMDGPU1:       return:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; AMDGPU1-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU1:       if.then:
; AMDGPU1-NEXT:    br label [[RETURN:%.*]]
; AMDGPU1:       if.end:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; AMDGPU1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; AMDGPU1-NEXT:    br label [[RETURN]]
; AMDGPU1:       return:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; AMDGPU1-SAME: () #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; AMDGPU1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU1:       user_code.entry:
; AMDGPU1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU1-NEXT:    ret void
; AMDGPU1:       worker.exit:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__16
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@weak_callee_empty
; AMDGPU1-SAME: () #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__17
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__18
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; AMDGPU1-SAME: () #[[ATTR6]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; AMDGPU1-SAME: () #[[ATTR1]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__19
; AMDGPU1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU1-NEXT:    ret void
;
;
; AMDGPU1: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU1-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; AMDGPU1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU1-NEXT:  entry:
; AMDGPU1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU1-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; NVPTX1-SAME: () #[[ATTR0:[0-9]+]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; NVPTX1-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; NVPTX1-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; NVPTX1-SAME: () #[[ATTR1:[0-9]+]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX1-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX1-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX1:       omp_if.then:
; NVPTX1-NEXT:    store i32 0, ptr @G, align 4
; NVPTX1-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX1-NEXT:    br label [[OMP_IF_END]]
; NVPTX1:       omp_if.end:
; NVPTX1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; NVPTX1-SAME: () #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX1-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX1-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX1:       omp_if.then:
; NVPTX1-NEXT:    store i32 0, ptr @G, align 4
; NVPTX1-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX1-NEXT:    br label [[OMP_IF_END]]
; NVPTX1:       omp_if.end:
; NVPTX1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__1
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__2
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__3
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__4
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; NVPTX1-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; NVPTX1-SAME: () #[[ATTR6:[0-9]+]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; NVPTX1-SAME: () #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__5
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; NVPTX1-SAME: () #[[ATTR6]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; NVPTX1-SAME: () #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__6
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__7
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__8
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__9
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__10
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__11
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__12
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__13
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__14
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__15
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; NVPTX1-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX1:       if.then:
; NVPTX1-NEXT:    br label [[RETURN:%.*]]
; NVPTX1:       if.end:
; NVPTX1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; NVPTX1-NEXT:    br label [[RETURN]]
; NVPTX1:       return:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; NVPTX1-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX1:       if.then:
; NVPTX1-NEXT:    br label [[RETURN:%.*]]
; NVPTX1:       if.end:
; NVPTX1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; NVPTX1-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; NVPTX1-NEXT:    br label [[RETURN]]
; NVPTX1:       return:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; NVPTX1-SAME: () #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; NVPTX1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX1:       user_code.entry:
; NVPTX1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_target_deinit()
; NVPTX1-NEXT:    ret void
; NVPTX1:       worker.exit:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__16
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@weak_callee_empty
; NVPTX1-SAME: () #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__17
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__18
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; NVPTX1-SAME: () #[[ATTR6]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline nounwind
; NVPTX1-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; NVPTX1-SAME: () #[[ATTR1]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__19
; NVPTX1-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX1-NEXT:    ret void
;
;
; NVPTX1: Function Attrs: convergent noinline norecurse nounwind
; NVPTX1-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; NVPTX1-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX1-NEXT:  entry:
; NVPTX1-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX1-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX1-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX1-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX1-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX1-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; AMDGPU2-SAME: () #[[ATTR0:[0-9]+]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; AMDGPU2-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; AMDGPU2-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; AMDGPU2-SAME: () #[[ATTR1:[0-9]+]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU2-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU2-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU2:       omp_if.then:
; AMDGPU2-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU2-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU2-NEXT:    br label [[OMP_IF_END]]
; AMDGPU2:       omp_if.end:
; AMDGPU2-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; AMDGPU2-SAME: () #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU2-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU2-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU2:       omp_if.then:
; AMDGPU2-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU2-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU2-NEXT:    br label [[OMP_IF_END]]
; AMDGPU2:       omp_if.end:
; AMDGPU2-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__1
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__2
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__3
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__4
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; AMDGPU2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; AMDGPU2-SAME: () #[[ATTR6:[0-9]+]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; AMDGPU2-SAME: () #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__5
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; AMDGPU2-SAME: () #[[ATTR6]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; AMDGPU2-SAME: () #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__6
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__7
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__8
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__9
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__10
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__11
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__12
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__13
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__14
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__15
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; AMDGPU2-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU2-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU2:       if.then:
; AMDGPU2-NEXT:    br label [[RETURN:%.*]]
; AMDGPU2:       if.end:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; AMDGPU2-NEXT:    br label [[RETURN]]
; AMDGPU2:       return:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; AMDGPU2-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU2-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU2:       if.then:
; AMDGPU2-NEXT:    br label [[RETURN:%.*]]
; AMDGPU2:       if.end:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; AMDGPU2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; AMDGPU2-NEXT:    br label [[RETURN]]
; AMDGPU2:       return:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; AMDGPU2-SAME: () #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; AMDGPU2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU2:       user_code.entry:
; AMDGPU2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU2-NEXT:    ret void
; AMDGPU2:       worker.exit:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__16
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@weak_callee_empty
; AMDGPU2-SAME: () #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__17
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__18
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; AMDGPU2-SAME: () #[[ATTR6]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; AMDGPU2-SAME: () #[[ATTR1]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__19
; AMDGPU2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU2: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU2-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; AMDGPU2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU2-NEXT:  entry:
; AMDGPU2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU2-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU2-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; AMDGPU3-SAME: () #[[ATTR0:[0-9]+]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; AMDGPU3-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; AMDGPU3-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; AMDGPU3-SAME: () #[[ATTR1:[0-9]+]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU3-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU3-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU3:       omp_if.then:
; AMDGPU3-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU3-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU3-NEXT:    br label [[OMP_IF_END]]
; AMDGPU3:       omp_if.end:
; AMDGPU3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; AMDGPU3-SAME: () #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU3-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; AMDGPU3-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; AMDGPU3:       omp_if.then:
; AMDGPU3-NEXT:    store i32 0, ptr @G, align 4
; AMDGPU3-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; AMDGPU3-NEXT:    br label [[OMP_IF_END]]
; AMDGPU3:       omp_if.end:
; AMDGPU3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__1
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__2
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__3
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__4
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; AMDGPU3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; AMDGPU3-SAME: () #[[ATTR6:[0-9]+]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; AMDGPU3-SAME: () #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__5
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; AMDGPU3-SAME: () #[[ATTR6]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; AMDGPU3-SAME: () #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__6
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__7
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__8
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__9
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__10
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__11
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__12
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__13
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__14
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p1() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__15
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; AMDGPU3-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU3-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU3:       if.then:
; AMDGPU3-NEXT:    br label [[RETURN:%.*]]
; AMDGPU3:       if.end:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; AMDGPU3-NEXT:    br label [[RETURN]]
; AMDGPU3:       return:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; AMDGPU3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; AMDGPU3-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; AMDGPU3:       if.then:
; AMDGPU3-NEXT:    br label [[RETURN:%.*]]
; AMDGPU3:       if.end:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; AMDGPU3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; AMDGPU3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; AMDGPU3-NEXT:    br label [[RETURN]]
; AMDGPU3:       return:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; AMDGPU3-SAME: () #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; AMDGPU3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; AMDGPU3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; AMDGPU3:       user_code.entry:
; AMDGPU3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_target_deinit()
; AMDGPU3-NEXT:    ret void
; AMDGPU3:       worker.exit:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__16
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@weak_callee_empty
; AMDGPU3-SAME: () #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__17
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__18
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; AMDGPU3-SAME: () #[[ATTR6]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; AMDGPU3-SAME: () #[[ATTR1]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; AMDGPU3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; AMDGPU3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__19
; AMDGPU3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @p0() #[[ATTR11]]
; AMDGPU3-NEXT:    ret void
;
;
; AMDGPU3: Function Attrs: convergent noinline norecurse nounwind
; AMDGPU3-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; AMDGPU3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; AMDGPU3-NEXT:  entry:
; AMDGPU3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; AMDGPU3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; AMDGPU3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; AMDGPU3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; AMDGPU3-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; AMDGPU3-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; NVPTX2-SAME: () #[[ATTR0:[0-9]+]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; NVPTX2-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; NVPTX2-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; NVPTX2-SAME: () #[[ATTR1:[0-9]+]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX2-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX2-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX2:       omp_if.then:
; NVPTX2-NEXT:    store i32 0, ptr @G, align 4
; NVPTX2-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX2-NEXT:    br label [[OMP_IF_END]]
; NVPTX2:       omp_if.end:
; NVPTX2-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; NVPTX2-SAME: () #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX2-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX2-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX2:       omp_if.then:
; NVPTX2-NEXT:    store i32 0, ptr @G, align 4
; NVPTX2-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX2-NEXT:    br label [[OMP_IF_END]]
; NVPTX2:       omp_if.end:
; NVPTX2-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__1
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__2
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__3
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__4
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; NVPTX2-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; NVPTX2-SAME: () #[[ATTR6:[0-9]+]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; NVPTX2-SAME: () #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__5
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; NVPTX2-SAME: () #[[ATTR6]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; NVPTX2-SAME: () #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__6
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__7
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__8
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__9
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__10
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__11
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__12
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__13
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__14
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__15
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; NVPTX2-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX2-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX2:       if.then:
; NVPTX2-NEXT:    br label [[RETURN:%.*]]
; NVPTX2:       if.end:
; NVPTX2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; NVPTX2-NEXT:    br label [[RETURN]]
; NVPTX2:       return:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; NVPTX2-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX2-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX2:       if.then:
; NVPTX2-NEXT:    br label [[RETURN:%.*]]
; NVPTX2:       if.end:
; NVPTX2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; NVPTX2-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; NVPTX2-NEXT:    br label [[RETURN]]
; NVPTX2:       return:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; NVPTX2-SAME: () #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; NVPTX2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX2:       user_code.entry:
; NVPTX2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_target_deinit()
; NVPTX2-NEXT:    ret void
; NVPTX2:       worker.exit:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__16
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@weak_callee_empty
; NVPTX2-SAME: () #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__17
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__18
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; NVPTX2-SAME: () #[[ATTR6]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline nounwind
; NVPTX2-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; NVPTX2-SAME: () #[[ATTR1]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__19
; NVPTX2-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX2: Function Attrs: convergent noinline norecurse nounwind
; NVPTX2-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; NVPTX2-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX2-NEXT:  entry:
; NVPTX2-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX2-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX2-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX2-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX2-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX2-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_needed_l14
; NVPTX3-SAME: () #[[ATTR0:[0-9]+]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3:[0-9]+]]
; NVPTX3-NEXT:    call void @__omp_outlined__(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9:[0-9]+]]
; NVPTX3-NEXT:    call void @unknown_no_openmp() #[[ATTR10:[0-9]+]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@no_parallel_region_in_here.internalized
; NVPTX3-SAME: () #[[ATTR1:[0-9]+]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX3-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX3-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX3:       omp_if.then:
; NVPTX3-NEXT:    store i32 0, ptr @G, align 4
; NVPTX3-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX3-NEXT:    br label [[OMP_IF_END]]
; NVPTX3:       omp_if.end:
; NVPTX3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@no_parallel_region_in_here
; NVPTX3-SAME: () #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX3-NEXT:    [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
; NVPTX3-NEXT:    br i1 [[TMP2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_END:%.*]]
; NVPTX3:       omp_if.then:
; NVPTX3-NEXT:    store i32 0, ptr @G, align 4
; NVPTX3-NEXT:    call void @__kmpc_end_single(ptr @[[GLOB2]], i32 [[TMP0]])
; NVPTX3-NEXT:    br label [[OMP_IF_END]]
; NVPTX3:       omp_if.end:
; NVPTX3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP0]])
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_l22
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_l22_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__1(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__1
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__2, ptr @__omp_outlined__2_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__3, ptr @__omp_outlined__3_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__2
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11:[0-9]+]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__2_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__2(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__3
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__3_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__3(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__4(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__4
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_before.internalized() #[[ATTR9]]
; NVPTX3-NEXT:    call void @no_parallel_region_in_here.internalized() #[[ATTR9]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__5, ptr @__omp_outlined__5_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_after.internalized() #[[ATTR9]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before.internalized
; NVPTX3-SAME: () #[[ATTR6:[0-9]+]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_before
; NVPTX3-SAME: () #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__17, ptr @__omp_outlined__17_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__5
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__5_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__5(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after.internalized
; NVPTX3-SAME: () #[[ATTR6]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_after
; NVPTX3-SAME: () #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__18, ptr @__omp_outlined__18_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__6(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__6
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__7, ptr @__omp_outlined__7_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    [[CALL:%.*]] = call i32 @unknown() #[[ATTR11]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__8, ptr @__omp_outlined__8_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__7
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__7_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__7(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__8
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__8_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__8(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__9(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__9
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__10, ptr @__omp_outlined__10_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__11, ptr @__omp_outlined__11_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__10
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__10_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__10(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__11
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__11_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__11(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_pure_l77
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__12(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__12
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS1:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    call void @unknown_no_openmp() #[[ATTR10]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__13, ptr @__omp_outlined__13_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 undef, i32 1, i32 -1, i32 -1, ptr @__omp_outlined__14, ptr @__omp_outlined__14_wrapper, ptr [[CAPTURED_VARS_ADDRS1]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__13
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__13_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__13(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__14
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p1() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__14_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__14(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__15(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__15
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[CALL:%.*]] = call i32 @omp_get_thread_num() #[[ATTR9]]
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[CALL]]) #[[ATTR9]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after.internalized
; NVPTX3-SAME: (i32 [[A:%.*]]) #[[ATTR6]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX3-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX3:       if.then:
; NVPTX3-NEXT:    br label [[RETURN:%.*]]
; NVPTX3:       if.end:
; NVPTX3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after.internalized(i32 [[SUB]]) #[[ATTR9]]
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after.internalized() #[[ATTR9]]
; NVPTX3-NEXT:    br label [[RETURN]]
; NVPTX3:       return:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after
; NVPTX3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[CMP:%.*]] = icmp eq i32 [[TMP0]], 0
; NVPTX3-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; NVPTX3:       if.then:
; NVPTX3-NEXT:    br label [[RETURN:%.*]]
; NVPTX3:       if.end:
; NVPTX3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
; NVPTX3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 1
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after(i32 [[SUB]]) #[[ATTR11]]
; NVPTX3-NEXT:    call void @simple_state_machine_interprocedural_nested_recursive_after_after() #[[ATTR11]]
; NVPTX3-NEXT:    br label [[RETURN]]
; NVPTX3:       return:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112
; NVPTX3-SAME: () #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112_kernel_environment)
; NVPTX3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
; NVPTX3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
; NVPTX3:       user_code.entry:
; NVPTX3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__omp_outlined__16(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_target_deinit()
; NVPTX3-NEXT:    ret void
; NVPTX3:       worker.exit:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__16
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @weak_callee_empty() #[[ATTR9]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@weak_callee_empty
; NVPTX3-SAME: () #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__17
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__17_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__17(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__18
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__18_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__18(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after.internalized
; NVPTX3-SAME: () #[[ATTR6]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]]) #[[ATTR3]]
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline nounwind
; NVPTX3-LABEL: define {{[^@]+}}@simple_state_machine_interprocedural_nested_recursive_after_after
; NVPTX3-SAME: () #[[ATTR1]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
; NVPTX3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
; NVPTX3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 -1, i32 -1, ptr @__omp_outlined__19, ptr @__omp_outlined__19_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 0)
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__19
; NVPTX3-SAME: (ptr noalias [[DOTGLOBAL_TID_:%.*]], ptr noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @p0() #[[ATTR11]]
; NVPTX3-NEXT:    ret void
;
;
; NVPTX3: Function Attrs: convergent noinline norecurse nounwind
; NVPTX3-LABEL: define {{[^@]+}}@__omp_outlined__19_wrapper
; NVPTX3-SAME: (i16 zeroext [[TMP0:%.*]], i32 [[TMP1:%.*]]) #[[ATTR0]] {
; NVPTX3-NEXT:  entry:
; NVPTX3-NEXT:    [[DOTADDR:%.*]] = alloca i16, align 2
; NVPTX3-NEXT:    [[DOTADDR1:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
; NVPTX3-NEXT:    [[GLOBAL_ARGS:%.*]] = alloca ptr, align 8
; NVPTX3-NEXT:    call void @__kmpc_get_shared_variables(ptr [[GLOBAL_ARGS]])
; NVPTX3-NEXT:    call void @__omp_outlined__19(ptr [[DOTADDR1]], ptr [[DOTZERO_ADDR]]) #[[ATTR3]]
; NVPTX3-NEXT:    ret void
;
;.
; AMDGPU1: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR3]] = { nounwind }
; AMDGPU1: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; AMDGPU1: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU1: attributes #[[ATTR9]] = { convergent nounwind }
; AMDGPU1: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; AMDGPU1: attributes #[[ATTR11]] = { convergent }
;.
; NVPTX1: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR3]] = { nounwind }
; NVPTX1: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; NVPTX1: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX1: attributes #[[ATTR9]] = { convergent nounwind }
; NVPTX1: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; NVPTX1: attributes #[[ATTR11]] = { convergent }
;.
; AMDGPU2: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR3]] = { nounwind }
; AMDGPU2: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; AMDGPU2: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU2: attributes #[[ATTR9]] = { convergent nounwind }
; AMDGPU2: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; AMDGPU2: attributes #[[ATTR11]] = { convergent }
;.
; AMDGPU3: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR3]] = { nounwind }
; AMDGPU3: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; AMDGPU3: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; AMDGPU3: attributes #[[ATTR9]] = { convergent nounwind }
; AMDGPU3: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; AMDGPU3: attributes #[[ATTR11]] = { convergent }
;.
; NVPTX2: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR3]] = { nounwind }
; NVPTX2: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; NVPTX2: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX2: attributes #[[ATTR9]] = { convergent nounwind }
; NVPTX2: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; NVPTX2: attributes #[[ATTR11]] = { convergent }
;.
; NVPTX3: attributes #[[ATTR0]] = { convergent noinline norecurse nounwind "frame-pointer"="none" "kernel" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR1]] = { convergent noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR2:[0-9]+]] = { convergent "frame-pointer"="none" "llvm.assume"="omp_no_openmp" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR3]] = { nounwind }
; NVPTX3: attributes #[[ATTR4:[0-9]+]] = { convergent "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR5:[0-9]+]] = { alwaysinline }
; NVPTX3: attributes #[[ATTR6]] = { noinline nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR7:[0-9]+]] = { convergent nounwind willreturn memory(read) "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR8:[0-9]+]] = { convergent nounwind "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+ptx32,+sm_20" }
; NVPTX3: attributes #[[ATTR9]] = { convergent nounwind }
; NVPTX3: attributes #[[ATTR10]] = { convergent "llvm.assume"="omp_no_openmp" }
; NVPTX3: attributes #[[ATTR11]] = { convergent }
;.
; AMDGPU1: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; AMDGPU1: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; AMDGPU1: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; AMDGPU1: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; AMDGPU1: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; AMDGPU1: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; AMDGPU1: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; AMDGPU1: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; AMDGPU1: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; AMDGPU1: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; AMDGPU1: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; AMDGPU1: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; AMDGPU1: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; AMDGPU1: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; AMDGPU1: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; AMDGPU1: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; AMDGPU1: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; AMDGPU1: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; AMDGPU1: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.
; NVPTX1: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; NVPTX1: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; NVPTX1: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; NVPTX1: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; NVPTX1: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; NVPTX1: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; NVPTX1: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; NVPTX1: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; NVPTX1: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; NVPTX1: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; NVPTX1: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; NVPTX1: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; NVPTX1: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; NVPTX1: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; NVPTX1: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; NVPTX1: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; NVPTX1: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; NVPTX1: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; NVPTX1: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.
; AMDGPU2: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; AMDGPU2: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; AMDGPU2: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; AMDGPU2: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; AMDGPU2: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; AMDGPU2: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; AMDGPU2: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; AMDGPU2: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; AMDGPU2: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; AMDGPU2: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; AMDGPU2: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; AMDGPU2: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; AMDGPU2: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; AMDGPU2: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; AMDGPU2: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; AMDGPU2: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; AMDGPU2: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; AMDGPU2: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; AMDGPU2: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.
; AMDGPU3: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; AMDGPU3: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; AMDGPU3: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; AMDGPU3: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; AMDGPU3: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; AMDGPU3: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; AMDGPU3: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; AMDGPU3: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; AMDGPU3: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; AMDGPU3: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; AMDGPU3: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; AMDGPU3: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; AMDGPU3: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; AMDGPU3: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; AMDGPU3: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; AMDGPU3: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; AMDGPU3: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; AMDGPU3: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; AMDGPU3: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.
; NVPTX2: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; NVPTX2: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; NVPTX2: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; NVPTX2: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; NVPTX2: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; NVPTX2: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; NVPTX2: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; NVPTX2: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; NVPTX2: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; NVPTX2: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; NVPTX2: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; NVPTX2: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; NVPTX2: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; NVPTX2: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; NVPTX2: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; NVPTX2: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; NVPTX2: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; NVPTX2: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; NVPTX2: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.
; NVPTX3: [[META0:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural", i32 39, i32 2}
; NVPTX3: [[META1:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_no_openmp_attr", i32 66, i32 4}
; NVPTX3: [[META2:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_needed", i32 14, i32 0}
; NVPTX3: [[META3:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_with_fallback", i32 55, i32 3}
; NVPTX3: [[META4:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_pure", i32 77, i32 5}
; NVPTX3: [[META5:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine_interprocedural_nested_recursive", i32 92, i32 6}
; NVPTX3: [[META6:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"no_state_machine_weak_callee", i32 112, i32 7}
; NVPTX3: [[META7:![0-9]+]] = !{i32 0, i32 20, i32 171331627, !"simple_state_machine", i32 22, i32 1}
; NVPTX3: [[META8:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_needed_l14, !"kernel", i32 1}
; NVPTX3: [[META9:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_l22, !"kernel", i32 1}
; NVPTX3: [[META10:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_l39, !"kernel", i32 1}
; NVPTX3: [[META11:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_with_fallback_l55, !"kernel", i32 1}
; NVPTX3: [[META12:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_no_openmp_attr_l66, !"kernel", i32 1}
; NVPTX3: [[META13:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_pure_l77, !"kernel", i32 1}
; NVPTX3: [[META14:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_simple_state_machine_interprocedural_nested_recursive_l92, !"kernel", i32 1}
; NVPTX3: [[META15:![0-9]+]] = !{ptr @__omp_offloading_14_a36502b_no_state_machine_weak_callee_l112, !"kernel", i32 1}
; NVPTX3: [[META16:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
; NVPTX3: [[META17:![0-9]+]] = !{i32 7, !"openmp", i32 50}
; NVPTX3: [[META18:![0-9]+]] = !{i32 7, !"openmp-device", i32 50}
;.