blob: da4c0f0acd6d49c5ef0978f0ecdcd8f6cf797129 [file] [log] [blame]
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS64
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC
# Test the long branch expansion of various branches
--- |
define i64 @expand_BNEZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BEQZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BNEC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BEQC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BLTC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BLTUC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BGEC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BGEUC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BLEZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BLTZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BGEZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
define i64 @expand_BGTZC64(i64 %a, i64 %b) {
%cmp = icmp eq i64 %a, %b
br i1 %cmp, label %iftrue, label %tail
iftrue:
call void asm sideeffect ".space 831068", ""()
ret i64 1
tail:
ret i64 0
}
...
---
name: expand_BNEZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BNEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS64: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; PIC: BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.2.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BNEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BEQZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BEQZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; MIPS64: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.2.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; PIC: BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
; PIC: bb.1.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.2.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BEQZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BNEC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BNEC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BEQC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BNEC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BEQC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BNEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BEQC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BEQC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BNEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BEQC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BNEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BEQC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BLTC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BLTC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BGEC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BGEC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BLTC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BLTUC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BLTUC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BGEUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTUC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BGEUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BLTUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BGEC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BGEC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BLTC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BLTC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BGEC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BGEUC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BGEUC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BLTUC64 $a0_64, $zero_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEUC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BLTUC64 $a0_64, $zero_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BGEUC64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BLEZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BLEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BGTZC64 $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BGTZC64 $a0_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BLEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BLTZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BLTZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BGEZC64 $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BLTZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BGEZC64 $a0_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BLTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BGEZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BGEZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BLTZC64 $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGEZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BLTZC64 $a0_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BGEZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...
---
name: expand_BGTZC64
alignment: 8
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
registers:
liveins:
- { reg: '$a0_64', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack:
stack:
constants:
body: |
; MIPS64-LABEL: name: expand_BGTZC64
; MIPS64: bb.0 (%ir-block.0):
; MIPS64: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; MIPS64: BLEZC64 $a0_64, %bb.2, implicit-def $at
; MIPS64: bb.1 (%ir-block.0):
; MIPS64: successors: %bb.3(0x80000000)
; MIPS64: J %bb.3, implicit-def $at {
; MIPS64: $zero = SLL $zero, 0
; MIPS64: }
; MIPS64: bb.2.iftrue:
; MIPS64: INLINEASM &".space 831068", 1
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 1
; MIPS64: }
; MIPS64: bb.3.tail:
; MIPS64: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; MIPS64: $v0_64 = DADDiu $zero_64, 0
; MIPS64: }
; PIC-LABEL: name: expand_BGTZC64
; PIC: bb.0 (%ir-block.0):
; PIC: successors: %bb.3(0x40000000), %bb.1(0x40000000)
; PIC: BLEZC64 $a0_64, %bb.3, implicit-def $at
; PIC: bb.1 (%ir-block.0):
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp_64 = DADDiu $sp_64, -16
; PIC: SD $ra_64, $sp_64, 0
; PIC: $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: $at_64 = DSLL $at_64, 16
; PIC: BAL_BR %bb.2, implicit-def $ra {
; PIC: $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
; PIC: $at_64 = DADDu $ra_64, $at_64
; PIC: $ra_64 = LD $sp_64, 0
; PIC: JR64 $at_64 {
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.iftrue:
; PIC: INLINEASM &".space 831068", 1
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 1
; PIC: }
; PIC: bb.4.tail:
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
; PIC: $v0_64 = DADDiu $zero_64, 0
; PIC: }
bb.0 (%ir-block.0):
successors: %bb.1(0x40000000), %bb.2(0x40000000)
liveins: $a0_64
BGTZC64 killed renamable $a0_64, %bb.2, implicit-def $at
bb.1.iftrue:
INLINEASM &".space 831068", 1
$v0_64 = DADDiu $zero_64, 1
PseudoReturn64 undef $ra_64, implicit killed $v0_64
bb.2.tail:
$v0_64 = DADDiu $zero_64, 0
PseudoReturn64 undef $ra_64, implicit killed $v0_64
...