commit 3874bb93bcc32f9ed0010c41c237933fc69ee17b
author Fraser Cormack <fraser@codeplay.com> Wed Feb 17 09:25:58 2021 +0000
committer Copybara-Service <copybara-worker@google.com> Fri Feb 19 03:26:58 2021 -0800
tree 70f516f510b4d352b96d496e6bcc3f0687c0e32b
parent 3eb36b48dbd28d1ddcfb55a1310297fd23164349

[SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes

This patch fixes a codegen crash introduced in fde24661718c, where the
DAGCombiner started generating optimized MULH[SU] or [SU]MUL_LOHI nodes
unless the target opted out. The AArch64 backend cannot currently select
any of these nodes, so ensure that they are not generated in the first
place.

This issue was raised by @huihuiz in D94501.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D96849

GitOrigin-RevId: 0176fecfbcd6b867fd31d7b85cc748220150babc

lib/Target/AArch64/AArch64ISelLowering.cpp

diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index ea6ec8a..e77868c 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1124,6 +1124,11 @@
       setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
+
+      setOperationAction(ISD::MULHU, VT, Expand);
+      setOperationAction(ISD::MULHS, VT, Expand);
+      setOperationAction(ISD::UMUL_LOHI, VT, Expand);
+      setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     }
 
     // Illegal unpacked integer vector types.

test/CodeGen/AArch64/sve-int-arith-imm.ll

diff --git a/test/CodeGen/AArch64/sve-int-arith-imm.ll b/test/CodeGen/AArch64/sve-int-arith-imm.ll
index 9cf22a3..ad47a4a 100644
--- a/test/CodeGen/AArch64/sve-int-arith-imm.ll
+++ b/test/CodeGen/AArch64/sve-int-arith-imm.ll
@@ -779,3 +779,27 @@
   %lshr = lshr <vscale x 2 x i64> %a, %splat
   ret <vscale x 2 x i64> %lshr
 }
+
+define <vscale x 4 x i32> @sdiv_const(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: sdiv_const:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov z1.s, #3 // =0x3
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    sdiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+entry:
+  %div = sdiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %div
+}
+
+define <vscale x 4 x i32> @udiv_const(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: udiv_const:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    mov z1.s, #3 // =0x3
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+entry:
+  %div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %div
+}