test/CodeGen/PowerPC/vec-zext-abdu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s

define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) {
; CHECK-LABEL: zext_abdu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; CHECK-NEXT:    xxlxor 36, 36, 36
; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; CHECK-NEXT:    lxv 37, 0(3)
; CHECK-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NEXT:    addi 3, 3, .LCPI0_1@toc@l
; CHECK-NEXT:    lxv 33, 0(3)
; CHECK-NEXT:    addis 3, 2, .LCPI0_2@toc@ha
; CHECK-NEXT:    vperm 0, 4, 2, 5
; CHECK-NEXT:    vperm 5, 4, 3, 5
; CHECK-NEXT:    addi 3, 3, .LCPI0_2@toc@l
; CHECK-NEXT:    lxv 39, 0(3)
; CHECK-NEXT:    vperm 6, 4, 2, 1
; CHECK-NEXT:    vperm 1, 4, 3, 1
; CHECK-NEXT:    vperm 2, 4, 2, 7
; CHECK-NEXT:    vperm 3, 4, 3, 7
; CHECK-NEXT:    xvnegsp 36, 38
; CHECK-NEXT:    xvnegsp 35, 35
; CHECK-NEXT:    xvnegsp 34, 34
; CHECK-NEXT:    vabsduw 2, 2, 3
; CHECK-NEXT:    xvnegsp 35, 33
; CHECK-NEXT:    vabsduw 3, 4, 3
; CHECK-NEXT:    xvnegsp 36, 37
; CHECK-NEXT:    xvnegsp 37, 32
; CHECK-NEXT:    vpkuwum 2, 2, 2
; CHECK-NEXT:    vabsduw 4, 5, 4
; CHECK-NEXT:    vpkuwum 3, 4, 3
; CHECK-NEXT:    vpkuhum 2, 2, 3
; CHECK-NEXT:    blr
entry:
  %aa = zext <12 x i8> %a to <12 x i32>
  %bb = zext <12 x i8> %b to <12 x i32>
  %s = sub nsw <12 x i32> %aa, %bb
  %c = icmp slt <12 x i32> %s, zeroinitializer
  %ss = sub nsw <12 x i32> zeroinitializer, %s
  %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s
  %ret = trunc <12 x i32> %sel to <12 x i8>
  ret <12 x i8> %ret
}