| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ |
| ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s |
| ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ |
| ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s |
| |
| ; Function Attrs: nounwind |
| define zeroext i8 @_Z6testcff(float %arg) { |
| ; CHECK-LABEL: _Z6testcff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptoui float %0 to i8 |
| ret i8 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z6testfcc(i8 zeroext %arg) { |
| ; CHECK-LABEL: _Z6testfcc: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stb r3, -1(r1) |
| ; CHECK-NEXT: xscvuxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i8, align 1 |
| store i8 %arg, i8* %arg.addr, align 1 |
| %0 = load i8, i8* %arg.addr, align 1 |
| %conv = uitofp i8 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i8 @_Z6testcdd(double %arg) { |
| ; CHECK-LABEL: _Z6testcdd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptoui double %0 to i8 |
| ret i8 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z6testdcc(i8 zeroext %arg) { |
| ; CHECK-LABEL: _Z6testdcc: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stb r3, -1(r1) |
| ; CHECK-NEXT: xscvuxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i8, align 1 |
| store i8 %arg, i8* %arg.addr, align 1 |
| %0 = load i8, i8* %arg.addr, align 1 |
| %conv = uitofp i8 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i8 @_Z7testucff(float %arg) { |
| ; CHECK-LABEL: _Z7testucff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptoui float %0 to i8 |
| ret i8 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z7testfuch(i8 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testfuch: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stb r3, -1(r1) |
| ; CHECK-NEXT: xscvuxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i8, align 1 |
| store i8 %arg, i8* %arg.addr, align 1 |
| %0 = load i8, i8* %arg.addr, align 1 |
| %conv = uitofp i8 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i8 @_Z7testucdd(double %arg) { |
| ; CHECK-LABEL: _Z7testucdd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptoui double %0 to i8 |
| ret i8 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z7testduch(i8 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testduch: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stb r3, -1(r1) |
| ; CHECK-NEXT: xscvuxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i8, align 1 |
| store i8 %arg, i8* %arg.addr, align 1 |
| %0 = load i8, i8* %arg.addr, align 1 |
| %conv = uitofp i8 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define signext i16 @_Z6testsff(float %arg) { |
| ; CHECK-LABEL: _Z6testsff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: extsw r3, r3 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptosi float %0 to i16 |
| ret i16 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z6testfss(i16 signext %arg) { |
| ; CHECK-LABEL: _Z6testfss: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwa f0, r3 |
| ; CHECK-NEXT: sth r3, -2(r1) |
| ; CHECK-NEXT: xscvsxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i16, align 2 |
| store i16 %arg, i16* %arg.addr, align 2 |
| %0 = load i16, i16* %arg.addr, align 2 |
| %conv = sitofp i16 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define signext i16 @_Z6testsdd(double %arg) { |
| ; CHECK-LABEL: _Z6testsdd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: extsw r3, r3 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptosi double %0 to i16 |
| ret i16 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z6testdss(i16 signext %arg) { |
| ; CHECK-LABEL: _Z6testdss: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwa f0, r3 |
| ; CHECK-NEXT: sth r3, -2(r1) |
| ; CHECK-NEXT: xscvsxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i16, align 2 |
| store i16 %arg, i16* %arg.addr, align 2 |
| %0 = load i16, i16* %arg.addr, align 2 |
| %conv = sitofp i16 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i16 @_Z7testusff(float %arg) { |
| ; CHECK-LABEL: _Z7testusff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptoui float %0 to i16 |
| ret i16 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z7testfust(i16 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testfust: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: sth r3, -2(r1) |
| ; CHECK-NEXT: xscvuxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i16, align 2 |
| store i16 %arg, i16* %arg.addr, align 2 |
| %0 = load i16, i16* %arg.addr, align 2 |
| %conv = uitofp i16 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i16 @_Z7testusdd(double %arg) { |
| ; CHECK-LABEL: _Z7testusdd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptoui double %0 to i16 |
| ret i16 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z7testdust(i16 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testdust: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: sth r3, -2(r1) |
| ; CHECK-NEXT: xscvuxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i16, align 2 |
| store i16 %arg, i16* %arg.addr, align 2 |
| %0 = load i16, i16* %arg.addr, align 2 |
| %conv = uitofp i16 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define signext i32 @_Z6testiff(float %arg) { |
| ; CHECK-LABEL: _Z6testiff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: extsw r3, r3 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptosi float %0 to i32 |
| ret i32 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z6testfii(i32 signext %arg) { |
| ; CHECK-LABEL: _Z6testfii: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwa f0, r3 |
| ; CHECK-NEXT: stw r3, -4(r1) |
| ; CHECK-NEXT: xscvsxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i32, align 4 |
| store i32 %arg, i32* %arg.addr, align 4 |
| %0 = load i32, i32* %arg.addr, align 4 |
| %conv = sitofp i32 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define signext i32 @_Z6testidd(double %arg) { |
| ; CHECK-LABEL: _Z6testidd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: extsw r3, r3 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptosi double %0 to i32 |
| ret i32 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z6testdii(i32 signext %arg) { |
| ; CHECK-LABEL: _Z6testdii: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwa f0, r3 |
| ; CHECK-NEXT: stw r3, -4(r1) |
| ; CHECK-NEXT: xscvsxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i32, align 4 |
| store i32 %arg, i32* %arg.addr, align 4 |
| %0 = load i32, i32* %arg.addr, align 4 |
| %conv = sitofp i32 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i32 @_Z7testuiff(float %arg) { |
| ; CHECK-LABEL: _Z7testuiff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpuxws f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptoui float %0 to i32 |
| ret i32 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z7testfuij(i32 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testfuij: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stw r3, -4(r1) |
| ; CHECK-NEXT: xscvuxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i32, align 4 |
| store i32 %arg, i32* %arg.addr, align 4 |
| %0 = load i32, i32* %arg.addr, align 4 |
| %conv = uitofp i32 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define zeroext i32 @_Z7testuidd(double %arg) { |
| ; CHECK-LABEL: _Z7testuidd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpuxws f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprwz r3, f0 |
| ; CHECK-NEXT: clrldi r3, r3, 32 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptoui double %0 to i32 |
| ret i32 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z7testduij(i32 zeroext %arg) { |
| ; CHECK-LABEL: _Z7testduij: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprwz f0, r3 |
| ; CHECK-NEXT: stw r3, -4(r1) |
| ; CHECK-NEXT: xscvuxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i32, align 4 |
| store i32 %arg, i32* %arg.addr, align 4 |
| %0 = load i32, i32* %arg.addr, align 4 |
| %conv = uitofp i32 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define i64 @_Z7testllff(float %arg) { |
| ; CHECK-LABEL: _Z7testllff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxds f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprd r3, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptosi float %0 to i64 |
| ret i64 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z7testfllx(i64 %arg) { |
| ; CHECK-LABEL: _Z7testfllx: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprd f0, r3 |
| ; CHECK-NEXT: std r3, -8(r1) |
| ; CHECK-NEXT: xscvsxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i64, align 8 |
| store i64 %arg, i64* %arg.addr, align 8 |
| %0 = load i64, i64* %arg.addr, align 8 |
| %conv = sitofp i64 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define i64 @_Z7testlldd(double %arg) { |
| ; CHECK-LABEL: _Z7testlldd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpsxds f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprd r3, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptosi double %0 to i64 |
| ret i64 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z7testdllx(i64 %arg) { |
| ; CHECK-LABEL: _Z7testdllx: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprd f0, r3 |
| ; CHECK-NEXT: std r3, -8(r1) |
| ; CHECK-NEXT: xscvsxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i64, align 8 |
| store i64 %arg, i64* %arg.addr, align 8 |
| %0 = load i64, i64* %arg.addr, align 8 |
| %conv = sitofp i64 %0 to double |
| ret double %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define i64 @_Z8testullff(float %arg) { |
| ; CHECK-LABEL: _Z8testullff: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpuxds f0, f1 |
| ; CHECK-NEXT: stfs f1, -4(r1) |
| ; CHECK-NEXT: mffprd r3, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca float, align 4 |
| store float %arg, float* %arg.addr, align 4 |
| %0 = load float, float* %arg.addr, align 4 |
| %conv = fptoui float %0 to i64 |
| ret i64 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define float @_Z8testfully(i64 %arg) { |
| ; CHECK-LABEL: _Z8testfully: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprd f0, r3 |
| ; CHECK-NEXT: std r3, -8(r1) |
| ; CHECK-NEXT: xscvuxdsp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i64, align 8 |
| store i64 %arg, i64* %arg.addr, align 8 |
| %0 = load i64, i64* %arg.addr, align 8 |
| %conv = uitofp i64 %0 to float |
| ret float %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define i64 @_Z8testulldd(double %arg) { |
| ; CHECK-LABEL: _Z8testulldd: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xscvdpuxds f0, f1 |
| ; CHECK-NEXT: stfd f1, -8(r1) |
| ; CHECK-NEXT: mffprd r3, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca double, align 8 |
| store double %arg, double* %arg.addr, align 8 |
| %0 = load double, double* %arg.addr, align 8 |
| %conv = fptoui double %0 to i64 |
| ret i64 %conv |
| } |
| |
| ; Function Attrs: nounwind |
| define double @_Z8testdully(i64 %arg) { |
| ; CHECK-LABEL: _Z8testdully: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: mtfprd f0, r3 |
| ; CHECK-NEXT: std r3, -8(r1) |
| ; CHECK-NEXT: xscvuxddp f1, f0 |
| ; CHECK-NEXT: blr |
| entry: |
| %arg.addr = alloca i64, align 8 |
| store i64 %arg, i64* %arg.addr, align 8 |
| %0 = load i64, i64* %arg.addr, align 8 |
| %conv = uitofp i64 %0 to double |
| ret double %conv |
| } |