commit 25b9afb5f4a06bea308fbc4623734652e7a1278c
author Fraser Cormack <fraser@codeplay.com> Fri Apr 16 10:58:41 2021 +0100
committer Copybara-Service <copybara-worker@google.com> Fri Apr 16 13:07:34 2021 -0700
tree 987fb0f96895bbf9b37f9a392d0e872b01016a3d
parent 239d7d0f1443d213645617918bf3c736ee72dda1

[RISCV] Rerun stack test through update_llc_test_checks.py

Adjusts formatting of comments only. Just to reduce diffs in future
patches.

GitOrigin-RevId: ec0f7c6923c1e6a722be6f4e0bb0e3d08b3bc3b1

test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll

diff --git a/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
index 67beafd..a00b85c 100644
--- a/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
+++ b/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
@@ -158,8 +158,8 @@
 ; CHECK-LABEL: lmul4_and_1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
-; CHECK-NEXT:    sd ra, 24(sp)  # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 16(sp)  # 8-byte Folded Spill
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 32
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    addi a1, zero, 5
@@ -167,8 +167,8 @@
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -32
-; CHECK-NEXT:    ld s0, 16(sp)  # 8-byte Folded Reload
-; CHECK-NEXT:    ld ra, 24(sp)  # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>
@@ -180,8 +180,8 @@
 ; CHECK-LABEL: lmul4_and_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi sp, sp, -32
-; CHECK-NEXT:    sd ra, 24(sp)  # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 16(sp)  # 8-byte Folded Spill
+; CHECK-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; CHECK-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    addi s0, sp, 32
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    addi a1, zero, 6
@@ -189,8 +189,8 @@
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    andi sp, sp, -32
 ; CHECK-NEXT:    addi sp, s0, -32
-; CHECK-NEXT:    ld s0, 16(sp)  # 8-byte Folded Reload
-; CHECK-NEXT:    ld ra, 24(sp)  # 8-byte Folded Reload
+; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 32
 ; CHECK-NEXT:    ret
   %v1 = alloca <vscale x 4 x i64>