| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s |
| |
| ; First, check the generic pattern for any 2 vector constants. Then, check special cases where |
| ; the constants are all off-by-one. Finally, check the extra special cases where the constants |
| ; include 0 or -1. |
| ; Each minimal select test is repeated with a more typical pattern that includes a compare to |
| ; generate the condition value. |
| |
| define <4 x i32> @sel_C1_or_C2_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_C1_or_C2_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI0_0 |
| ; CHECK-NEXT: adrp x9, .LCPI0_1 |
| ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] |
| ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1] |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: sshr v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_C1_or_C2_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_C1_or_C2_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI1_0 |
| ; CHECK-NEXT: adrp x9, .LCPI1_1 |
| ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_0] |
| ; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI1_1] |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 3000, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_Cplus1_or_C_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_Cplus1_or_C_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI2_0 |
| ; CHECK-NEXT: adrp x9, .LCPI2_1 |
| ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] |
| ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI2_1] |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: sshr v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_Cplus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_Cplus1_or_C_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI3_0 |
| ; CHECK-NEXT: adrp x9, .LCPI3_1 |
| ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0] |
| ; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI3_1] |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 42, i32 0, i32 -2, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_Cminus1_or_C_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_Cminus1_or_C_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI4_0 |
| ; CHECK-NEXT: adrp x9, .LCPI4_1 |
| ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] |
| ; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI4_1] |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: sshr v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: bsl v0.16b, v2.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_Cminus1_or_C_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_Cminus1_or_C_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: adrp x8, .LCPI5_0 |
| ; CHECK-NEXT: adrp x9, .LCPI5_1 |
| ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI5_0] |
| ; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI5_1] |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 43, i32 1, i32 -1, i32 0>, <4 x i32> <i32 44, i32 2, i32 0, i32 1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_minus1_or_0_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_minus1_or_0_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: sshr v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_minus1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_minus1_or_0_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_0_or_minus1_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_0_or_minus1_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: cmge v0.4s, v0.4s, #0 |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_0_or_minus1_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: mvn v0.16b, v0.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_1_or_0_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: sshr v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: movi v1.4s, #1 |
| ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_1_or_0_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_1_or_0_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: movi v1.4s, #1 |
| ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @sel_0_or_1_vec(<4 x i1> %cond) { |
| ; CHECK-LABEL: sel_0_or_1_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ushll v0.4s, v0.4h, #0 |
| ; CHECK-NEXT: shl v0.4s, v0.4s, #31 |
| ; CHECK-NEXT: cmge v0.4s, v0.4s, #0 |
| ; CHECK-NEXT: movi v1.4s, #1 |
| ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b |
| ; CHECK-NEXT: ret |
| %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> |
| ret <4 x i32> %add |
| } |
| |
| define <4 x i32> @cmp_sel_0_or_1_vec(<4 x i32> %x, <4 x i32> %y) { |
| ; CHECK-LABEL: cmp_sel_0_or_1_vec: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s |
| ; CHECK-NEXT: movi v1.4s, #1 |
| ; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b |
| ; CHECK-NEXT: ret |
| %cond = icmp eq <4 x i32> %x, %y |
| %add = select <4 x i1> %cond, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> <i32 1, i32 1, i32 1, i32 1> |
| ret <4 x i32> %add |
| } |
| |