| ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s |
| |
| ;;; Test vector equivalence intrinsic instructions |
| ;;; |
| ;;; Note: |
| ;;; We test VEQV*vvl, VEQV*vvl_v, VEQV*rvl, VEQV*rvl_v, VEQV*vvml_v, |
| ;;; VEQV*rvml_v, PVEQV*vvl, PVEQV*vvl_v, PVEQV*rvl, PVEQV*rvl_v, PVEQV*vvml_v, |
| ;;; and PVEQV*rvml_v instructions. |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: veqv_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: veqv %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: veqv_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: veqv %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: veqv_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: veqv %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: veqv_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: veqv %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: veqv_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: veqv %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @veqv_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: veqv_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: veqv %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: pveqv_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pveqv %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pveqv_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pveqv %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: pveqv_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pveqv %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pveqv_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pveqv %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pveqv_vvvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pveqv %v2, %v0, %v1, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pveqv_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pveqv_vsvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pveqv %v1, %s0, %v0, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) |