| ; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s |
| |
| ;;; Test vector add intrinsic instructions |
| ;;; |
| ;;; Note: |
| ;;; We test VADD*ivl, VADD*ivl_v, VADD*ivml_v, VADD*rvl, VADD*rvl_v, |
| ;;; VADD*rvml_v, VADD*vvl, VADD*vvl_v, VADD*vvml_v PVADD*vvl, PVADD*vvl_v, |
| ;;; PVADD*rvl, PVADD*rvl_v, PVADD*vvml_v, and PVADD*rvml_v instructions. |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddsl_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.l %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvl_imm(<256 x double> %0) { |
| ; CHECK-LABEL: vaddsl_vsvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v0, 8, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %2 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64 8, <256 x double> %0, i32 256) |
| ret <256 x double> %2 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddsl_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.l %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddsl_vsvmvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v1, 8, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddsl_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.l %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddsl_vsvvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v1, 8, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddsl_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddsl_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddsl_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.l %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvl(i32 signext %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswsx_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvl_imm(<256 x double> %0) { |
| ; CHECK-LABEL: vaddswsx_vsvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v0, 8, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %2 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32 8, <256 x double> %0, i32 256) |
| ret <256 x double> %2 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddswsx_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.sx %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswsx_vsvmvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v1, 8, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswsx_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.sx %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswsx_vsvvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v1, 8, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswsx_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddswsx_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswsx_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.sx %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvl(i32 signext %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswzx_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.zx %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvl_imm(<256 x double> %0) { |
| ; CHECK-LABEL: vaddswzx_vsvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v0, 8, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %2 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32 8, <256 x double> %0, i32 256) |
| ret <256 x double> %2 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddswzx_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.zx %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswzx_vsvmvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v1, 8, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswzx_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vadds.w.zx %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswzx_vsvvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v1, 8, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddswzx_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddswzx_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddswzx_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vadds.w.zx %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddul_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.l %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvl_imm(<256 x double> %0) { |
| ; CHECK-LABEL: vaddul_vsvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v0, 8, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %2 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvl(i64 8, <256 x double> %0, i32 256) |
| ret <256 x double> %2 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddul_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.l %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddul_vsvmvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v1, 8, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddul_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.l %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vsvvl_imm(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddul_vsvvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v1, 8, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vaddul_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vaddul_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vaddul_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vaddul_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.l %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vaddul.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvl(i32 signext %0, <256 x double> %1) { |
| ; CHECK-LABEL: vadduw_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.w %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvl(i32 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vsvl(i32, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvl_imm(<256 x double> %0) { |
| ; CHECK-LABEL: vadduw_vsvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v0, 8, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %2 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvl(i32 8, <256 x double> %0, i32 256) |
| ret <256 x double> %2 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vadduw_vsvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.w %v1, %s0, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vadduw_vsvmvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v1, 8, %v0, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vadduw_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: and %s0, %s0, (32)0 |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: vaddu.w %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vsvvl_imm(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vadduw_vsvvl_imm: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v1, 8, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: vadduw_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: vadduw_vvvmvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v2, %v0, %v1, %vm1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @vadduw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: vadduw_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: vaddu.w %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.vadduw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: pvaddu_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvaddu %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pvaddu_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvaddu %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: pvaddu_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvaddu %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pvaddu_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvaddu %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pvaddu_vvvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvaddu %v2, %v0, %v1, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvaddu_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pvaddu_vsvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvaddu %v1, %s0, %v0, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvaddu.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vvvl(<256 x double> %0, <256 x double> %1) { |
| ; CHECK-LABEL: pvadds_vvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 256 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvadds %v0, %v0, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvl(<256 x double> %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vvvl(<256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pvadds_vvvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvadds %v2, %v0, %v1 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vsvl(i64 %0, <256 x double> %1) { |
| ; CHECK-LABEL: pvadds_vsvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 256 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvadds %v0, %s0, %v0 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %3 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvl(i64 %0, <256 x double> %1, i32 256) |
| ret <256 x double> %3 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vsvl(i64, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { |
| ; CHECK-LABEL: pvadds_vsvvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvadds %v1, %s0, %v0 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %4 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) |
| ret <256 x double> %4 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vsvvl(i64, <256 x double>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pvadds_vvvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s0, 128 |
| ; CHECK-NEXT: lvl %s0 |
| ; CHECK-NEXT: pvadds %v2, %v0, %v1, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v2 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) |
| |
| ; Function Attrs: nounwind readnone |
| define fastcc <256 x double> @pvadds_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { |
| ; CHECK-LABEL: pvadds_vsvMvl: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: lea %s1, 128 |
| ; CHECK-NEXT: lvl %s1 |
| ; CHECK-NEXT: pvadds %v1, %s0, %v0, %vm2 |
| ; CHECK-NEXT: lea %s16, 256 |
| ; CHECK-NEXT: lvl %s16 |
| ; CHECK-NEXT: vor %v0, (0)1, %v1 |
| ; CHECK-NEXT: b.l.t (, %s10) |
| %5 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) |
| ret <256 x double> %5 |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <256 x double> @llvm.ve.vl.pvadds.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) |