| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s |
| |
| --- | |
| define hidden arm_aapcs_vfpcc void @it_block_store_count_before_start(float* %pSrc, float* %pDst, i32 %blockSize, i32* %iter.addr) #0 { |
| entry: |
| %mul = shl i32 %blockSize, 1 |
| %0 = add i32 %mul, 3 |
| %1 = icmp slt i32 %mul, 4 |
| %smin = select i1 %1, i32 %mul, i32 4 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 2 |
| %4 = add nuw nsw i32 %3, 1 |
| store i32 %4, i32* %iter.addr, align 4 |
| %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) |
| br label %do.body |
| |
| do.body: ; preds = %do.body, %entry |
| %lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %start, %entry ] |
| %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ] |
| %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ] |
| %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ] |
| %pDst.addr.01 = bitcast float* %pDst.addr.0 to <4 x float>* |
| %pSrc.addr.02 = bitcast float* %pSrc.addr.0 to <4 x float>* |
| %5 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) |
| %6 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.02, i32 4, <4 x i1> %5, <4 x float> undef) |
| %7 = fmul <4 x float> %6, %6 |
| tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %7, <4 x float>* %pDst.addr.01, i32 4, <4 x i1> %5) |
| %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4 |
| %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4 |
| %sub = add nsw i32 %blkCnt.0, -4 |
| %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1) |
| %9 = icmp ne i32 %8, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv, -1 |
| br i1 %9, label %do.body, label %do.end |
| |
| do.end: ; preds = %do.body |
| ret void |
| } |
| |
| define hidden arm_aapcs_vfpcc void @it_block_store_count_after_start(float* %pSrc, float* %pDst, i32 %blockSize, i32* %iter.addr) #0 { |
| entry: |
| %mul = shl i32 %blockSize, 1 |
| %0 = add i32 %mul, 3 |
| %1 = icmp slt i32 %mul, 4 |
| %smin = select i1 %1, i32 %mul, i32 4 |
| %2 = sub i32 %0, %smin |
| %3 = lshr i32 %2, 2 |
| %4 = add nuw nsw i32 %3, 1 |
| %start = call i32 @llvm.start.loop.iterations.i32(i32 %4) |
| store i32 %4, i32* %iter.addr, align 4 |
| br label %do.body |
| |
| do.body: ; preds = %do.body, %entry |
| %lsr.iv = phi i32 [ %lsr.iv.next, %do.body ], [ %start, %entry ] |
| %blkCnt.0 = phi i32 [ %mul, %entry ], [ %sub, %do.body ] |
| %pDst.addr.0 = phi float* [ %pDst, %entry ], [ %add.ptr4, %do.body ] |
| %pSrc.addr.0 = phi float* [ %pSrc, %entry ], [ %add.ptr, %do.body ] |
| %pDst.addr.01 = bitcast float* %pDst.addr.0 to <4 x float>* |
| %pSrc.addr.02 = bitcast float* %pSrc.addr.0 to <4 x float>* |
| %5 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) |
| %6 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.02, i32 4, <4 x i1> %5, <4 x float> undef) |
| %7 = fmul <4 x float> %6, %6 |
| tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %7, <4 x float>* %pDst.addr.01, i32 4, <4 x i1> %5) |
| %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4 |
| %add.ptr4 = getelementptr inbounds float, float* %pDst.addr.0, i32 4 |
| %sub = add nsw i32 %blkCnt.0, -4 |
| %8 = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1) |
| %9 = icmp ne i32 %8, 0 |
| %lsr.iv.next = add nsw i32 %lsr.iv, -1 |
| br i1 %9, label %do.body, label %do.end |
| |
| do.end: ; preds = %do.body |
| ret void |
| } |
| |
| ; Function Attrs: nounwind readnone |
| declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1 |
| |
| ; Function Attrs: argmemonly nounwind readonly willreturn |
| declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) #2 |
| |
| ; Function Attrs: argmemonly nounwind willreturn writeonly |
| declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32 immarg, <4 x i1>) #3 |
| |
| ; Function Attrs: noduplicate nounwind |
| declare i32 @llvm.start.loop.iterations.i32(i32) #4 |
| |
| ; Function Attrs: noduplicate nounwind |
| declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4 |
| |
| attributes #0 = { "target-features"="+mve.fp" } |
| attributes #1 = { nounwind readnone "target-features"="+mve.fp" } |
| attributes #2 = { argmemonly nounwind readonly willreturn "target-features"="+mve.fp" } |
| attributes #3 = { argmemonly nounwind willreturn writeonly "target-features"="+mve.fp" } |
| attributes #4 = { noduplicate nounwind "target-features"="+mve.fp" } |
| |
| ... |
| --- |
| name: it_block_store_count_before_start |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: it_block_store_count_before_start |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 11, 8, implicit-def $itstate |
| ; CHECK: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate |
| ; CHECK: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) |
| ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.do.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r12 |
| ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.02, align 4) |
| ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16 into %ir.pDst.addr.01, align 4) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.do.end: |
| ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r3, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg |
| t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 11, 8, implicit-def $itstate |
| $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate |
| renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg |
| renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg |
| t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) |
| $lr = t2DoLoopStart renamable $lr |
| $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg |
| |
| bb.1.do.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r12 |
| |
| $lr = tMOVr $r2, 14 /* CC::al */, $noreg |
| renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg |
| renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.02, align 4) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, undef renamable $q0 |
| MVE_VPST 8, implicit $vpr |
| renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16 into %ir.pDst.addr.01, align 4) |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.do.end: |
| frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |
| --- |
| name: it_block_store_count_after_start |
| alignment: 2 |
| tracksRegLiveness: true |
| registers: [] |
| liveins: |
| - { reg: '$r0', virtual-reg: '' } |
| - { reg: '$r1', virtual-reg: '' } |
| - { reg: '$r2', virtual-reg: '' } |
| - { reg: '$r3', virtual-reg: '' } |
| frameInfo: |
| stackSize: 8 |
| offsetAdjustment: 0 |
| maxAlignment: 4 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: |
| - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, |
| stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true, |
| debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } |
| callSites: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| ; CHECK-LABEL: name: it_block_store_count_after_start |
| ; CHECK: bb.0.entry: |
| ; CHECK: successors: %bb.1(0x80000000) |
| ; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r7 |
| ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 |
| ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 |
| ; CHECK: renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: t2IT 11, 8, implicit-def $itstate |
| ; CHECK: $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate |
| ; CHECK: renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) |
| ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg |
| ; CHECK: bb.1.do.body: |
| ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| ; CHECK: liveins: $r0, $r1, $r2, $r12 |
| ; CHECK: $lr = tMOVr $r2, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg |
| ; CHECK: renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg |
| ; CHECK: renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.02, align 4) |
| ; CHECK: renamable $q0 = MVE_VMULf32 killed renamable $q0, killed renamable $q0, 0, $noreg, undef renamable $q0 |
| ; CHECK: MVE_VPST 8, implicit $vpr |
| ; CHECK: renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16 into %ir.pDst.addr.01, align 4) |
| ; CHECK: dead $lr = t2LEUpdate killed renamable $lr, %bb.1 |
| ; CHECK: bb.2.do.end: |
| ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| bb.0.entry: |
| successors: %bb.1(0x80000000) |
| liveins: $r0, $r1, $r2, $r3, $r7, $lr |
| |
| frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp |
| frame-setup CFI_INSTRUCTION def_cfa_offset 8 |
| frame-setup CFI_INSTRUCTION offset $lr, -4 |
| frame-setup CFI_INSTRUCTION offset $r7, -8 |
| renamable $lr = t2MOVi 4, 14 /* CC::al */, $noreg, $noreg |
| renamable $r12 = t2LSLri renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg |
| t2CMPri renamable $r12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| t2IT 11, 8, implicit-def $itstate |
| $lr = t2LSLri renamable $r2, 1, 11 /* CC::lt */, killed $cpsr, $noreg, implicit killed renamable $lr, implicit killed $itstate |
| renamable $r2 = t2RSBrs killed renamable $lr, killed renamable $r2, 10, 14 /* CC::al */, $noreg, $noreg |
| renamable $lr = t2ADDri killed renamable $r2, 3, 14 /* CC::al */, $noreg, $noreg |
| renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg |
| renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg |
| t2STRi12 renamable $lr, killed renamable $r3, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.iter.addr) |
| $lr = t2DoLoopStart renamable $lr |
| $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg |
| |
| bb.1.do.body: |
| successors: %bb.1(0x7c000000), %bb.2(0x04000000) |
| liveins: $r0, $r1, $r2, $r12 |
| |
| $lr = tMOVr $r2, 14 /* CC::al */, $noreg |
| renamable $vpr = MVE_VCTP32 renamable $r12, 0, $noreg |
| renamable $r2, dead $cpsr = nsw tSUBi8 killed $r2, 1, 14 /* CC::al */, $noreg |
| renamable $r12 = nsw t2SUBri killed renamable $r12, 4, 14 /* CC::al */, $noreg, $noreg |
| MVE_VPST 8, implicit $vpr |
| renamable $r0, renamable $q0 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.02, align 4) |
| renamable $lr = t2LoopDec killed renamable $lr, 1 |
| renamable $q0 = MVE_VMULf32 killed renamable $q0, renamable $q0, 0, $noreg, undef renamable $q0 |
| MVE_VPST 8, implicit $vpr |
| renamable $r1 = MVE_VSTRWU32_post killed renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr :: (store 16 into %ir.pDst.addr.01, align 4) |
| t2LoopEnd killed renamable $lr, %bb.1, implicit-def dead $cpsr |
| tB %bb.2, 14 /* CC::al */, $noreg |
| |
| bb.2.do.end: |
| frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc |
| |
| ... |