| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| |
| # Check that we remove hints during selection. |
| |
| ... |
| --- |
| name: assert_zext_gpr |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: assert_zext_gpr |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: %copy:gpr32all = COPY $w0 |
| ; CHECK: $w1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:gpr(s32) = COPY $w0 |
| %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16 |
| $w1 = COPY %copy_assert_zext(s32) |
| RET_ReallyLR implicit $w1 |
| |
| ... |
| --- |
| name: assert_zext_fpr |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $s0, $s1 |
| |
| ; CHECK-LABEL: name: assert_zext_fpr |
| ; CHECK: liveins: $s0, $s1 |
| ; CHECK: %copy:fpr32 = COPY $s0 |
| ; CHECK: $s1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $s1 |
| %copy:fpr(s32) = COPY $s0 |
| %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16 |
| $s1 = COPY %copy_assert_zext(s32) |
| RET_ReallyLR implicit $s1 |
| |
| ... |
| --- |
| name: assert_zext_in_between_cross_bank |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $s0, $w1 |
| |
| ; CHECK-LABEL: name: assert_zext_in_between_cross_bank |
| ; CHECK: liveins: $s0, $w1 |
| ; CHECK: %copy:fpr32 = COPY $s0 |
| ; CHECK: $w1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:fpr(s32) = COPY $s0 |
| %copy_assert_zext:fpr(s32) = G_ASSERT_ZEXT %copy, 16 |
| $w1 = COPY %copy_assert_zext(s32) |
| RET_ReallyLR implicit $w1 |
| |
| ... |
| --- |
| name: assert_zext_decided_dst_class |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1, $w2 |
| |
| ; Users of G_ASSERT_ZEXT may end up deciding the destination register class. |
| ; Make sure that the source register class is constrained. |
| |
| ; CHECK-LABEL: name: assert_zext_decided_dst_class |
| ; CHECK: liveins: $w0, $w1, $w2 |
| ; CHECK: %copy_with_rc:gpr32sp = COPY $w2 |
| ; CHECK: $w1 = COPY %copy_with_rc |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:gpr(s32) = COPY $w0 |
| %copy_assert_zext:gpr(s32) = G_ASSERT_ZEXT %copy, 16 |
| %copy_with_rc:gpr32sp(s32) = COPY $w2 |
| $w1 = COPY %copy_with_rc(s32) |
| RET_ReallyLR implicit $w1 |
| |
| ... |
| --- |
| name: assert_sext_gpr |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1 |
| |
| ; CHECK-LABEL: name: assert_sext_gpr |
| ; CHECK: liveins: $w0, $w1 |
| ; CHECK: %copy:gpr32all = COPY $w0 |
| ; CHECK: $w1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:gpr(s32) = COPY $w0 |
| %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16 |
| $w1 = COPY %copy_assert_sext(s32) |
| RET_ReallyLR implicit $w1 |
| |
| ... |
| --- |
| name: assert_sext_fpr |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $s0, $s1 |
| |
| ; CHECK-LABEL: name: assert_sext_fpr |
| ; CHECK: liveins: $s0, $s1 |
| ; CHECK: %copy:fpr32 = COPY $s0 |
| ; CHECK: $s1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $s1 |
| %copy:fpr(s32) = COPY $s0 |
| %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16 |
| $s1 = COPY %copy_assert_sext(s32) |
| RET_ReallyLR implicit $s1 |
| |
| ... |
| --- |
| name: assert_sext_in_between_cross_bank |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $s0, $w1 |
| |
| ; CHECK-LABEL: name: assert_sext_in_between_cross_bank |
| ; CHECK: liveins: $s0, $w1 |
| ; CHECK: %copy:fpr32 = COPY $s0 |
| ; CHECK: $w1 = COPY %copy |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:fpr(s32) = COPY $s0 |
| %copy_assert_sext:fpr(s32) = G_ASSERT_SEXT %copy, 16 |
| $w1 = COPY %copy_assert_sext(s32) |
| RET_ReallyLR implicit $w1 |
| |
| ... |
| --- |
| name: assert_sext_decided_dst_class |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1, $w2 |
| |
| ; Users of G_ASSERT_SEXT may end up deciding the destination register class. |
| ; Make sure that the source register class is constrained. |
| |
| ; CHECK-LABEL: name: assert_sext_decided_dst_class |
| ; CHECK: liveins: $w0, $w1, $w2 |
| ; CHECK: %copy_with_rc:gpr32sp = COPY $w2 |
| ; CHECK: $w1 = COPY %copy_with_rc |
| ; CHECK: RET_ReallyLR implicit $w1 |
| %copy:gpr(s32) = COPY $w0 |
| %copy_assert_sext:gpr(s32) = G_ASSERT_SEXT %copy, 16 |
| %copy_with_rc:gpr32sp(s32) = COPY $w2 |
| $w1 = COPY %copy_with_rc(s32) |
| RET_ReallyLR implicit $w1 |