[AMDGPU] Add GFX11.5 s_singleuse_vdst instruction (#67536)
GitOrigin-RevId: 2a0ec5f1acfad2d407c1c8076f03a83094ca30dd
diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td
index 924144c..bf5a7b0 100644
--- a/lib/Target/AMDGPU/AMDGPU.td
+++ b/lib/Target/AMDGPU/AMDGPU.td
@@ -797,6 +797,12 @@
"Has SALU floating point instructions"
>;
+def FeatureVGPRSingleUseHintInsts : SubtargetFeature<"vgpr-singleuse-hint",
+ "HasVGPRSingleUseHintInsts",
+ "true",
+ "Has single-use VGPR hint instructions"
+>;
+
//===------------------------------------------------------------===//
// Subtarget Features (options and debugging)
//===------------------------------------------------------------===//
@@ -1390,12 +1396,14 @@
def FeatureISAVersion11_5_0 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[FeatureSALUFloatInsts,
- FeatureDPPSrc1SGPR])>;
+ FeatureDPPSrc1SGPR,
+ FeatureVGPRSingleUseHintInsts])>;
def FeatureISAVersion11_5_1 : FeatureSet<
!listconcat(FeatureISAVersion11_Common.Features,
[FeatureSALUFloatInsts,
FeatureDPPSrc1SGPR,
+ FeatureVGPRSingleUseHintInsts,
FeatureGFX11FullVGPRs])>;
//===----------------------------------------------------------------------===//
@@ -1909,6 +1917,9 @@
def HasSALUFloatInsts : Predicate<"Subtarget->hasSALUFloatInsts()">,
AssemblerPredicate<(all_of FeatureSALUFloatInsts)>;
+def HasVGPRSingleUseHintInsts : Predicate<"Subtarget->hasVGPRSingleUseHintInsts()">,
+ AssemblerPredicate<(all_of FeatureVGPRSingleUseHintInsts)>;
+
def HasGDS : Predicate<"Subtarget->hasGDS()">;
def HasGWS : Predicate<"Subtarget->hasGWS()">;
diff --git a/lib/Target/AMDGPU/GCNSubtarget.h b/lib/Target/AMDGPU/GCNSubtarget.h
index e7d46c0..ce538f0 100644
--- a/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/lib/Target/AMDGPU/GCNSubtarget.h
@@ -194,6 +194,7 @@
bool HasPackedTID = false;
bool ScalarizeGlobal = false;
bool HasSALUFloatInsts = false;
+ bool HasVGPRSingleUseHintInsts = false;
bool HasVcmpxPermlaneHazard = false;
bool HasVMEMtoScalarWriteHazard = false;
@@ -1145,6 +1146,8 @@
bool hasSALUFloatInsts() const { return HasSALUFloatInsts; }
+ bool hasVGPRSingleUseHintInsts() const { return HasVGPRSingleUseHintInsts; }
+
/// Return the maximum number of waves per SIMD for kernels using \p SGPRs
/// SGPRs
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
diff --git a/lib/Target/AMDGPU/SOPInstructions.td b/lib/Target/AMDGPU/SOPInstructions.td
index 90b89e9..f330904 100644
--- a/lib/Target/AMDGPU/SOPInstructions.td
+++ b/lib/Target/AMDGPU/SOPInstructions.td
@@ -1558,6 +1558,11 @@
"$simm16">;
} // End SubtargetPredicate = isGFX11Plus
+let SubtargetPredicate = HasVGPRSingleUseHintInsts in {
+ def S_SINGLEUSE_VDST :
+ SOPP_Pseudo<"s_singleuse_vdst", (ins s16imm:$simm16), "$simm16">;
+} // End SubtargetPredicate = HasVGPRSingeUseHintInsts
+
//===----------------------------------------------------------------------===//
// SOP1 Patterns
//===----------------------------------------------------------------------===//
@@ -2268,6 +2273,12 @@
defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>;
//===----------------------------------------------------------------------===//
+// SOPP - GFX1150
+//===----------------------------------------------------------------------===//
+
+defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11<0x013>;
+
+//===----------------------------------------------------------------------===//
// SOPP - GFX6, GFX7, GFX8, GFX9, GFX10
//===----------------------------------------------------------------------===//
diff --git a/test/MC/AMDGPU/gfx1150_asm_sopp.s b/test/MC/AMDGPU/gfx1150_asm_sopp.s
new file mode 100644
index 0000000..463e9ca
--- /dev/null
+++ b/test/MC/AMDGPU/gfx1150_asm_sopp.s
@@ -0,0 +1,10 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1150 -show-encoding %s | FileCheck --check-prefixes=GFX1150 %s
+
+s_singleuse_vdst 0x0000
+// GFX1150: encoding: [0x00,0x00,0x93,0xbf]
+
+s_singleuse_vdst 0xffff
+// GFX1150: encoding: [0xff,0xff,0x93,0xbf]
+
+s_singleuse_vdst 0x1234
+// GFX1150: encoding: [0x34,0x12,0x93,0xbf]
diff --git a/test/MC/AMDGPU/gfx11_unsupported.s b/test/MC/AMDGPU/gfx11_unsupported.s
index 5e9714b..3b1b7e4 100644
--- a/test/MC/AMDGPU/gfx11_unsupported.s
+++ b/test/MC/AMDGPU/gfx11_unsupported.s
@@ -1980,3 +1980,6 @@
s_cmp_nlt_f16 s1, s2
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
+s_singleuse_vdst 0x1234
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
diff --git a/test/MC/Disassembler/AMDGPU/decode-err.txt b/test/MC/Disassembler/AMDGPU/decode-err.txt
index 8da7e5a..bf2c55e 100644
--- a/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -5,6 +5,10 @@
# GCN: warning: invalid instruction encoding
0xdf,0x00,0x00,0x02
+# this is s_singleuse_vdst 0x1234, which is only valid on gfx1150
+# GFX11: warning: invalid instruction encoding
+0x34,0x12,0x93,0xbf
+
# this is buffer_atomic_csub_u32 v5, off, s[8:11], s3 offset:4095. Invalid without glc
# GFX11: warning: invalid instruction encoding
0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03
diff --git a/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt b/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
new file mode 100644
index 0000000..ddeb70a
--- /dev/null
+++ b/test/MC/Disassembler/AMDGPU/gfx1150_dasm_sopp.txt
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx1150 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1150 %s
+
+# GFX1150: s_singleuse_vdst 0x0 ; encoding: [0x00,0x00,0x93,0xbf]
+0x00,0x00,0x93,0xbf
+
+# GFX1150: s_singleuse_vdst 0xffff ; encoding: [0xff,0xff,0x93,0xbf]
+0xff,0xff,0x93,0xbf
+
+# GFX1150: s_singleuse_vdst 0x1234 ; encoding: [0x34,0x12,0x93,0xbf]
+0x34,0x12,0x93,0xbf
