test/CodeGen/RISCV/rvv-cfi-info.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=OMIT-FP %s
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs -frame-pointer=all < %s \
; RUN:   | FileCheck -check-prefix=NO-OMIT-FP %s

define riscv_vector_cc <vscale x 1 x i32> @test_vector_callee_cfi(<vscale x 1 x i32> %va) {
; OMIT-FP-LABEL: test_vector_callee_cfi:
; OMIT-FP:       # %bb.0: # %entry
; OMIT-FP-NEXT:    addi sp, sp, -16
; OMIT-FP-NEXT:    .cfi_def_cfa_offset 16
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    slli a0, a0, 3
; OMIT-FP-NEXT:    sub sp, sp, a0
; OMIT-FP-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    li a1, 6
; OMIT-FP-NEXT:    mul a0, a0, a1
; OMIT-FP-NEXT:    add a0, sp, a0
; OMIT-FP-NEXT:    addi a0, a0, 16
; OMIT-FP-NEXT:    vs1r.v v1, (a0) # Unknown-size Folded Spill
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    slli a0, a0, 2
; OMIT-FP-NEXT:    add a0, sp, a0
; OMIT-FP-NEXT:    addi a0, a0, 16
; OMIT-FP-NEXT:    vs2r.v v2, (a0) # Unknown-size Folded Spill
; OMIT-FP-NEXT:    addi a0, sp, 16
; OMIT-FP-NEXT:    vs4r.v v4, (a0) # Unknown-size Folded Spill
; OMIT-FP-NEXT:    .cfi_escape 0x10, 0x61, 0x08, 0x11, 0x7e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v1 @ cfa - 2 * vlenb
; OMIT-FP-NEXT:    .cfi_escape 0x10, 0x62, 0x08, 0x11, 0x7c, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v2m2 @ cfa - 4 * vlenb
; OMIT-FP-NEXT:    .cfi_escape 0x10, 0x64, 0x08, 0x11, 0x78, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v4m4 @ cfa - 8 * vlenb
; OMIT-FP-NEXT:    #APP
; OMIT-FP-NEXT:    #NO_APP
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    li a1, 6
; OMIT-FP-NEXT:    mul a0, a0, a1
; OMIT-FP-NEXT:    add a0, sp, a0
; OMIT-FP-NEXT:    addi a0, a0, 16
; OMIT-FP-NEXT:    vl1r.v v1, (a0) # Unknown-size Folded Reload
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    slli a0, a0, 2
; OMIT-FP-NEXT:    add a0, sp, a0
; OMIT-FP-NEXT:    addi a0, a0, 16
; OMIT-FP-NEXT:    vl2r.v v2, (a0) # Unknown-size Folded Reload
; OMIT-FP-NEXT:    addi a0, sp, 16
; OMIT-FP-NEXT:    vl4r.v v4, (a0) # Unknown-size Folded Reload
; OMIT-FP-NEXT:    csrr a0, vlenb
; OMIT-FP-NEXT:    slli a0, a0, 3
; OMIT-FP-NEXT:    add sp, sp, a0
; OMIT-FP-NEXT:    addi sp, sp, 16
; OMIT-FP-NEXT:    ret
;
; NO-OMIT-FP-LABEL: test_vector_callee_cfi:
; NO-OMIT-FP:       # %bb.0: # %entry
; NO-OMIT-FP-NEXT:    addi sp, sp, -32
; NO-OMIT-FP-NEXT:    .cfi_def_cfa_offset 32
; NO-OMIT-FP-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
; NO-OMIT-FP-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
; NO-OMIT-FP-NEXT:    .cfi_offset ra, -8
; NO-OMIT-FP-NEXT:    .cfi_offset s0, -16
; NO-OMIT-FP-NEXT:    addi s0, sp, 32
; NO-OMIT-FP-NEXT:    .cfi_def_cfa s0, 0
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 3
; NO-OMIT-FP-NEXT:    sub sp, sp, a0
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 1
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vs1r.v v1, (a0) # Unknown-size Folded Spill
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 2
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vs2r.v v2, (a0) # Unknown-size Folded Spill
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 3
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vs4r.v v4, (a0) # Unknown-size Folded Spill
; NO-OMIT-FP-NEXT:    .cfi_escape 0x10, 0x61, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x7e, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v1 @ cfa - 32 - 2 * vlenb
; NO-OMIT-FP-NEXT:    .cfi_escape 0x10, 0x62, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x7c, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v2m2 @ cfa - 32 - 4 * vlenb
; NO-OMIT-FP-NEXT:    .cfi_escape 0x10, 0x64, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x78, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # $v4m4 @ cfa - 32 - 8 * vlenb
; NO-OMIT-FP-NEXT:    #APP
; NO-OMIT-FP-NEXT:    #NO_APP
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 1
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vl1r.v v1, (a0) # Unknown-size Folded Reload
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 2
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vl2r.v v2, (a0) # Unknown-size Folded Reload
; NO-OMIT-FP-NEXT:    csrr a0, vlenb
; NO-OMIT-FP-NEXT:    slli a0, a0, 3
; NO-OMIT-FP-NEXT:    sub a0, s0, a0
; NO-OMIT-FP-NEXT:    addi a0, a0, -32
; NO-OMIT-FP-NEXT:    vl4r.v v4, (a0) # Unknown-size Folded Reload
; NO-OMIT-FP-NEXT:    addi sp, s0, -32
; NO-OMIT-FP-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
; NO-OMIT-FP-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
; NO-OMIT-FP-NEXT:    addi sp, sp, 32
; NO-OMIT-FP-NEXT:    ret
entry:
  call void asm sideeffect "",
  "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"()

  ret <vscale x 1 x i32> %va
}