| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s |
| |
| define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv4i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m4 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 4 x i32> @extract_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv4i32_4: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv2r.v v8, v10 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv2i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m4 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv2i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v9 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 2) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv2i32_4: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v10 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 4) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv8i32_nxv2i32_6: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v11 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 6) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv8i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m8 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) |
| ret <vscale x 8 x i32> %c |
| } |
| |
| define <vscale x 8 x i32> @extract_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv8i32_8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv4r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) |
| ret <vscale x 8 x i32> %c |
| } |
| |
| define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv4i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v8m8 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv4i32_4: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv2r.v v8, v10 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv4i32_8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv2r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 4 x i32> @extract_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv4i32_12: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv2r.v v8, v14 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12) |
| ret <vscale x 4 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v9 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_4: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v10 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 4) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_6: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v11 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 6) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v12 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 8) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_10: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v13 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 10) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_12: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v14 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 12) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 2 x i32> @extract_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv2i32_14: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v15 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 14) |
| ret <vscale x 2 x i32> %c |
| } |
| |
| define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv1i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v8m8 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 0) |
| ret <vscale x 1 x i32> %c |
| } |
| |
| ; TODO: Extracts that don't align to a vector register are not yet supported. |
| ; In this case we want to extract the upper half of the lowest VR subregister |
| ; in the LMUL group. |
| ; define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec) { |
| ; %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 1) |
| ; ret <vscale x 1 x i32> %c |
| ; } |
| |
| define <vscale x 1 x i32> @extract_nxv16i32_nxv1i32_2(<vscale x 16 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv16i32_nxv1i32_2: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v8, v9 |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 2) |
| ret <vscale x 1 x i32> %c |
| } |
| |
| define <vscale x 1 x i32> @extract_nxv2i32_nxv1i32_0(<vscale x 2 x i32> %vec) { |
| ; CHECK-LABEL: extract_nxv2i32_nxv1i32_0: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: ret |
| %c = call <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 0) |
| ret <vscale x 1 x i32> %c |
| } |
| |
| declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv2i32(<vscale x 2 x i32> %vec, i64 %idx) |
| |
| declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx) |
| declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, i64 %idx) |
| |
| declare <vscale x 1 x i32> @llvm.experimental.vector.extract.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) |
| declare <vscale x 2 x i32> @llvm.experimental.vector.extract.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) |
| declare <vscale x 4 x i32> @llvm.experimental.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) |
| declare <vscale x 8 x i32> @llvm.experimental.vector.extract.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, i64 %idx) |