| # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py |
| # RUN: llvm-mca -mtriple=thumbv7-m.main-none-none-eabi -mcpu=cortex-m7 -mattr=+fp64 -instruction-tables < %s | FileCheck %s |
| |
| vabs.f32 s0, s2 |
| vabs.f64 d0, d2 |
| vadd.f32 s0, s2, s1 |
| vadd.f64 d0, d2, d1 |
| vcmp.f32 s1, s2 |
| vcmp.f64 d1, d2 |
| vcvt.f32.f64 s1, d2 |
| vcvt.f64.f32 d1, s1 |
| vcvt.f32.u16 s1, s2, #8 |
| vcvt.f32.s16 s1, s2, #8 |
| vcvt.f32.u32 s1, s2, #8 |
| vcvt.f32.s32 s1, s2, #8 |
| vcvt.u16.f32 s1, s2, #8 |
| vcvt.s16.f32 s1, s2, #8 |
| vcvt.u32.f32 s1, s2, #8 |
| vcvt.s32.f32 s1, s2, #8 |
| vcvt.f64.u16 d1, d2, #8 |
| vcvt.f64.s16 d1, d2, #8 |
| vcvt.f64.u32 d1, d2, #8 |
| vcvt.f64.s32 d1, d2, #8 |
| vcvt.u16.f64 d1, d2, #8 |
| vcvt.s16.f64 d1, d2, #8 |
| vcvt.u32.f64 d1, d2, #8 |
| vcvt.s32.f64 d1, d2, #8 |
| vcvt.u32.f32 s1, s2 |
| vcvt.s32.f32 s1, s2 |
| vcvt.u32.f64 s1, d2 |
| vcvt.s32.f64 s1, d2 |
| vcvt.f32.u32 s1, s2 |
| vcvt.f32.s32 s1, s2 |
| vcvt.f64.u32 d1, s2 |
| vcvt.f64.s32 d1, s2 |
| vcvta.u32.f32 s1, s2 |
| vcvta.s32.f32 s1, s2 |
| vcvta.u32.f64 s1, d2 |
| vcvta.s32.f64 s1, d2 |
| vcvtm.u32.f32 s1, s2 |
| vcvtm.s32.f32 s1, s2 |
| vcvtm.u32.f64 s1, d2 |
| vcvtm.s32.f64 s1, d2 |
| vcvtn.u32.f32 s1, s2 |
| vcvtn.s32.f32 s1, s2 |
| vcvtn.u32.f64 s1, d2 |
| vcvtn.s32.f64 s1, d2 |
| vcvtp.u32.f32 s1, s2 |
| vcvtp.s32.f32 s1, s2 |
| vcvtp.u32.f64 s1, d2 |
| vcvtp.s32.f64 s1, d2 |
| vcvtb.f32.f16 s1, s2 |
| vcvtb.f16.f32 s1, s2 |
| vcvtr.u32.f32 s1, s2 |
| vcvtr.s32.f32 s1, s2 |
| vcvtr.u32.f64 s1, d2 |
| vcvtr.s32.f64 s1, d2 |
| vcvtt.f16.f32 s1, s2 |
| vcvtt.f32.f16 s1, s2 |
| vdiv.f32 s0, s2, s1 |
| vdiv.f64 d0, d2, d1 |
| vfma.f32 s0, s2, s1 |
| vfma.f64 d0, d2, d1 |
| vfms.f32 s0, s2, s1 |
| vfms.f64 d0, d2, d1 |
| vfnma.f32 s0, s2, s1 |
| vfnma.f64 d0, d2, d1 |
| vfnms.f32 s0, s2, s1 |
| vfnms.f64 d0, d2, d1 |
| vmaxnm.f32 s0, s2, s1 |
| vmaxnm.f64 d0, d2, d1 |
| vminnm.f32 s0, s2, s1 |
| vminnm.f64 d0, d2, d1 |
| vmla.f32 s0, s2, s1 |
| vmla.f64 d0, d2, d1 |
| vmls.f32 s0, s2, s1 |
| vmls.f64 d0, d2, d1 |
| vmov.f32 s0, r1 |
| vmov.f32 r0, s1 |
| vmov.f64 d0, r1, r2 |
| vmov.f64 r0, r1, d1 |
| vmov s0, s1, r0, r1 |
| vmov r0, r1, s0, s1 |
| vmov.f32 s0, #1.0 |
| vmov.f64 d0, #1.0 |
| vmov.f32 s0, s1 |
| vmov.f64 d0, d1 |
| vmul.f32 s0, s2, s1 |
| vmul.f64 d0, d2, d1 |
| vneg.f32 s0, s2 |
| vneg.f64 d0, d2 |
| vnmla.f32 s0, s2, s1 |
| vnmla.f64 d0, d2, d1 |
| vnmls.f32 s0, s2, s1 |
| vnmls.f64 d0, d2, d1 |
| vnmul.f32 s0, s2, s1 |
| vnmul.f64 d0, d2, d1 |
| vrinta.f32.f32 s0, s2 |
| vrinta.f64.f64 d0, d2 |
| vrintm.f32.f32 s0, s2 |
| vrintm.f64.f64 d0, d2 |
| vrintn.f32.f32 s0, s2 |
| vrintn.f64.f64 d0, d2 |
| vrintp.f32.f32 s0, s2 |
| vrintp.f64.f64 d0, d2 |
| vrintr.f32.f32 s0, s2 |
| vrintr.f64.f64 d0, d2 |
| vrintz.f32.f32 s0, s2 |
| vrintz.f64.f64 d0, d2 |
| vrintx.f32.f32 s0, s2 |
| vrintx.f64.f64 d0, d2 |
| vseleq.f32 s0, s2, s1 |
| vseleq.f64 d0, d2, d1 |
| vsqrt.f32 s0, s2 |
| vsqrt.f64 d0, d2 |
| vsub.f32 s0, s2, s1 |
| vsub.f64 d0, d2, d1 |
| |
| vldr.f64 d0, [r0] |
| vldr.f32 s0, [r0] |
| vstr.f64 d0, [r0] |
| vstr.f32 s0, [r0] |
| |
| # CHECK: Instruction Info: |
| # CHECK-NEXT: [1]: #uOps |
| # CHECK-NEXT: [2]: Latency |
| # CHECK-NEXT: [3]: RThroughput |
| # CHECK-NEXT: [4]: MayLoad |
| # CHECK-NEXT: [5]: MayStore |
| # CHECK-NEXT: [6]: HasSideEffects (U) |
| |
| # CHECK: [1] [2] [3] [4] [5] [6] Instructions: |
| # CHECK-NEXT: 1 3 1.00 vabs.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vabs.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vadd.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 4 1.00 vadd.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 0 1.00 vcmp.f32 s1, s2 |
| # CHECK-NEXT: 1 0 1.00 vcmp.f64 d1, d2 |
| # CHECK-NEXT: 1 4 1.00 vcvt.f32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.f32 d1, s1 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.u16 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.s16 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.u32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.s32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u16.f32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s16.f32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u32.f32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s32.f32 s1, s1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.u16 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.s16 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.u32 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.s32 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u16.f64 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s16.f64 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u32.f64 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s32.f64 d1, d1, #8 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.u32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f32.s32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.u32 d1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvt.f64.s32 d1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvta.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvta.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 4 1.00 vcvta.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 4 1.00 vcvta.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtm.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtm.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 4 1.00 vcvtm.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 4 1.00 vcvtm.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtn.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtn.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 4 1.00 vcvtn.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 4 1.00 vcvtn.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtp.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtp.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 4 1.00 vcvtp.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 4 1.00 vcvtp.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtb.f32.f16 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtb.f16.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtr.u32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtr.s32.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtr.u32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtr.s32.f64 s1, d2 |
| # CHECK-NEXT: 1 3 1.00 vcvtt.f16.f32 s1, s2 |
| # CHECK-NEXT: 1 3 1.00 vcvtt.f32.f16 s1, s2 |
| # CHECK-NEXT: 1 16 1.00 vdiv.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 30 1.00 vdiv.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vfma.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vfma.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vfms.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vfms.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vfnma.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vfnma.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vfnms.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vfnms.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 vmaxnm.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 4 1.00 vmaxnm.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 vminnm.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 4 1.00 vminnm.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vmla.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vmla.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vmls.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vmls.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 0.50 vmov s0, r1 |
| # CHECK-NEXT: 1 3 0.50 vmov r0, s1 |
| # CHECK-NEXT: 1 3 1.00 vmov d0, r1, r2 |
| # CHECK-NEXT: 1 3 1.00 vmov r0, r1, d1 |
| # CHECK-NEXT: 1 3 1.00 vmov s0, s1, r0, r1 |
| # CHECK-NEXT: 1 3 1.00 vmov r0, r1, s0, s1 |
| # CHECK-NEXT: 1 3 0.50 vmov.f32 s0, #1.000000e+00 |
| # CHECK-NEXT: 1 3 1.00 vmov.f64 d0, #1.000000e+00 |
| # CHECK-NEXT: 1 3 0.50 vmov.f32 s0, s1 |
| # CHECK-NEXT: 1 3 1.00 vmov.f64 d0, d1 |
| # CHECK-NEXT: 1 3 1.00 vmul.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 7 1.00 vmul.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 vneg.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vneg.f64 d0, d2 |
| # CHECK-NEXT: 1 6 1.00 vnmla.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vnmla.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 6 1.00 vnmls.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 11 1.00 vnmls.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 vnmul.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 7 1.00 vnmul.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 vrinta.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrinta.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintm.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintm.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintn.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintn.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintp.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintp.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintr.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintr.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintz.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintz.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vrintx.f32 s0, s2 |
| # CHECK-NEXT: 1 4 1.00 vrintx.f64 d0, d2 |
| # CHECK-NEXT: 1 4 1.00 vseleq.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 5 1.00 vseleq.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 16 1.00 vsqrt.f32 s0, s2 |
| # CHECK-NEXT: 1 30 1.00 vsqrt.f64 d0, d2 |
| # CHECK-NEXT: 1 3 1.00 vsub.f32 s0, s2, s1 |
| # CHECK-NEXT: 1 4 1.00 vsub.f64 d0, d2, d1 |
| # CHECK-NEXT: 1 3 1.00 * vldr d0, [r0] |
| # CHECK-NEXT: 1 2 0.50 * vldr s0, [r0] |
| # CHECK-NEXT: 1 2 1.00 * vstr d0, [r0] |
| # CHECK-NEXT: 1 2 1.00 * vstr s0, [r0] |
| |
| # CHECK: Resources: |
| # CHECK-NEXT: [0.0] - M7UnitALU |
| # CHECK-NEXT: [0.1] - M7UnitALU |
| # CHECK-NEXT: [1] - M7UnitBranch |
| # CHECK-NEXT: [2.0] - M7UnitLoad |
| # CHECK-NEXT: [2.1] - M7UnitLoad |
| # CHECK-NEXT: [3] - M7UnitMAC |
| # CHECK-NEXT: [4] - M7UnitSIMD |
| # CHECK-NEXT: [5] - M7UnitShift1 |
| # CHECK-NEXT: [6] - M7UnitShift2 |
| # CHECK-NEXT: [7] - M7UnitStore |
| # CHECK-NEXT: [8] - M7UnitVFP |
| # CHECK-NEXT: [9.0] - M7UnitVPort |
| # CHECK-NEXT: [9.1] - M7UnitVPort |
| |
| # CHECK: Resource pressure per iteration: |
| # CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] |
| # CHECK-NEXT: - - - 1.00 1.00 - - - - 2.00 104.00 81.00 81.00 |
| |
| # CHECK: Resource pressure by instruction: |
| # CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions: |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vabs.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vadd.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcmp.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcmp.f64 d1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvt.f32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.f32 d1, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u16 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s16 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f32 s1, s1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u16 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s16 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f64 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f64 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 d1, d1, #8 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f32.f16 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f16.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f64 s1, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f16.f32 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f32.f16 s1, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vdiv.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vdiv.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfma.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfma.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfms.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfms.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnma.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnma.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnms.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnms.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmaxnm.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmaxnm.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vminnm.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vminnm.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmla.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmla.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmls.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmls.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov s0, r1 |
| # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, s1 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov d0, r1, r2 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, d1 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov s0, s1, r0, r1 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, s0, s1 |
| # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, #1.000000e+00 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, #1.000000e+00 |
| # CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, s1 |
| # CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmul.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmul.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vneg.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vneg.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmla.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmla.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmls.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmls.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmul.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmul.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrinta.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrinta.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintm.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintm.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintn.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintn.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintp.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintp.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintr.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintr.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintz.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintz.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintx.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintx.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vseleq.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vseleq.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsqrt.f32 s0, s2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsqrt.f64 d0, d2 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f32 s0, s2, s1 |
| # CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsub.f64 d0, d2, d1 |
| # CHECK-NEXT: - - - 0.50 0.50 - - - - - - 1.00 1.00 vldr d0, [r0] |
| # CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr s0, [r0] |
| # CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 1.00 vstr d0, [r0] |
| # CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr s0, [r0] |
