test/CodeGen/ARM/GlobalISel/select-pr35926.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple arm-gnueabihf -mattr=+vfp4 -run-pass=instruction-select -o - %s | FileCheck %s
--- |
  declare double @llvm.fma.f64(double, double, double) #0

  define double @vfnmsd(double %x, double %y, double %z) #1 {
    %minus.y = fsub double -0.000000e+00, %y
    %fma = tail call double @llvm.fma.f64(double %x, double %minus.y, double %z)
    %minus.fma = fsub double -0.000000e+00, %fma
    ret double %minus.fma
  }

  ; Function Attrs: nounwind
  declare void @llvm.stackprotector(i8*, i8**) #2

  attributes #0 = { nounwind readnone speculatable "target-features"="+vfp4" }
  attributes #1 = { "target-features"="+vfp4" }
  attributes #2 = { nounwind }

...
---
name:            vfnmsd
legalized:       true
regBankSelected: true
selected:        false
body:             |
  bb.1 (%ir-block.0):
    liveins: $d0, $d1, $d2

    ; CHECK-LABEL: name: vfnmsd
    ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
    ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
    ; CHECK: [[VFNMSD:%[0-9]+]]:dpr = VFNMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
    ; CHECK: $d0 = COPY [[VFNMSD]]
    ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $d0
    %0:fprb(s64) = COPY $d0
    %1:fprb(s64) = COPY $d1
    %2:fprb(s64) = COPY $d2
    %3:fprb(s64) = G_FNEG %1
    %4:fprb(s64) = G_FMA %0, %3, %2
    %5:fprb(s64) = G_FNEG %4
    $d0 = COPY %5(s64)
    MOVPCLR 14, $noreg, implicit $d0


...