test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-fast -o -  %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regbankselect -regbankselect-greedy -o - %s | FileCheck %s

---
name: ashr_s32_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: ashr_s32_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s32) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: ashr_s32_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: ashr_s32_sv
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY2]], [[COPY1]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s32) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: ashr_s32_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: ashr_s32_vs
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY]], [[COPY2]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $sgpr0
    %2:_(s32) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: ashr_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: ashr_s32_vv
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: ashr_s16_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: ashr_s16_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)
    ; CHECK: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s16)
    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[SEXT]], [[ZEXT]](s32)
    ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[ASHR]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[TRUNC2]](s16)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $sgpr1
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_ASHR %2, %3
    S_ENDPGM 0, implicit %4
...

---
name: ashr_s16_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; CHECK-LABEL: name: ashr_s16_sv
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[COPY2]], [[TRUNC1]](s16)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s16)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = COPY $vgpr0
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_ASHR %2, %3
    S_ENDPGM 0, implicit %4
...

---
name: ashr_s16_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: ashr_s16_vs
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY2]](s16)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s16)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $sgpr0
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_ASHR %2, %3
    S_ENDPGM 0, implicit %4

...

---
name: ashr_s16_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: ashr_s16_vv
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s16)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s16) = G_TRUNC %0
    %3:_(s16) = G_TRUNC %1
    %4:_(s16) = G_ASHR %2, %3
    S_ENDPGM 0, implicit %4

...

---
name: ashr_v2s16_ss
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1
    ; CHECK-LABEL: name: ashr_v2s16_ss
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
    ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
    ; CHECK: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST]], 16
    ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
    ; CHECK: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST]], [[C]](s32)
    ; CHECK: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[BITCAST1]], 16
    ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16
    ; CHECK: [[ASHR1:%[0-9]+]]:sgpr(s32) = G_ASHR [[BITCAST1]], [[C1]](s32)
    ; CHECK: [[ASHR2:%[0-9]+]]:sgpr(s32) = G_ASHR [[SEXT_INREG]], [[SEXT_INREG1]](s32)
    ; CHECK: [[ASHR3:%[0-9]+]]:sgpr(s32) = G_ASHR [[ASHR]], [[ASHR1]](s32)
    ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ASHR2]](s32), [[ASHR3]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[BUILD_VECTOR_TRUNC]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $sgpr0
    %1:_(<2 x s16>) = COPY $sgpr1
    %2:_(<2 x s16>) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2

...

---
name: ashr_v2s16_sv
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: ashr_v2s16_sv
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY]](<2 x s16>)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY2]], [[COPY1]](<2 x s16>)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $sgpr0
    %1:_(<2 x s16>) = COPY $vgpr0
    %2:_(<2 x s16>) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: ashr_v2s16_vs
legalized: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0
    ; CHECK-LABEL: name: ashr_v2s16_vs
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[COPY1]](<2 x s16>)
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY2]](<2 x s16>)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $sgpr0
    %2:_(<2 x s16>) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2

...

---
name: ashr_v2s16_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: ashr_v2s16_vv
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
    ; CHECK: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
    %0:_(<2 x s16>) = COPY $vgpr0
    %1:_(<2 x s16>) = COPY $vgpr1
    %2:_(<2 x s16>) = G_ASHR %0, %1
    S_ENDPGM 0, implicit %2

...