test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s

# GFX6/7 selection should fail.
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s

---
name:            atomicrmw_fadd_s32_local
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local
    ; GFX8: liveins: $vgpr0, $vgpr1
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: $m0 = S_MOV_B32 -1
    ; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; GFX6: $m0 = S_MOV_B32 -1
    ; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
    ; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)
    $vgpr0 = COPY %2

...

---
name:            atomicrmw_fadd_s32_local_noret
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local_noret
    ; GFX8: liveins: $vgpr0, $vgpr1
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: $m0 = S_MOV_B32 -1
    ; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local_noret
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local_noret
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; GFX6: $m0 = S_MOV_B32 -1
    ; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)

...

---
name:            atomicrmw_fadd_s32_local_gep4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: atomicrmw_fadd_s32_local_gep4
    ; GFX8: liveins: $vgpr0, $vgpr1
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: $m0 = S_MOV_B32 -1
    ; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 4, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
    ; GFX9-LABEL: name: atomicrmw_fadd_s32_local_gep4
    ; GFX9: liveins: $vgpr0, $vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
    ; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
    ; GFX6-LABEL: name: atomicrmw_fadd_s32_local_gep4
    ; GFX6: liveins: $vgpr0, $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; GFX6: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4
    ; GFX6: [[PTR_ADD:%[0-9]+]]:vgpr(p3) = G_PTR_ADD [[COPY]], [[C]](s32)
    ; GFX6: $m0 = S_MOV_B32 -1
    ; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[PTR_ADD]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
    ; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
    %0:vgpr(p3) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = G_CONSTANT i32 4
    %3:vgpr(p3) = G_PTR_ADD %0, %2
    %4:vgpr(s32) = G_ATOMICRMW_FADD %3(p3), %1 :: (load store seq_cst 4, addrspace 3)
    $vgpr0 = COPY %4

...