test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=HSAPAL %s
# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=HSAPAL %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=MESA %s

---
name: groupstaticsize_v
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  ldsSize: 4096

body: |
  bb.0:

    ; HSAPAL-LABEL: name: groupstaticsize_v
    ; HSAPAL: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
    ; HSAPAL: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
    ; MESA-LABEL: name: groupstaticsize_v
    ; MESA: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize, implicit $exec
    ; MESA: S_ENDPGM 0, implicit [[V_MOV_B32_e32_]]
    %0:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
    S_ENDPGM 0, implicit %0
...

---
name: groupstaticsize_s
legalized: true
regBankSelected: true
tracksRegLiveness: true
machineFunctionInfo:
  ldsSize: 1024

body: |
  bb.0:

    ; HSAPAL-LABEL: name: groupstaticsize_s
    ; HSAPAL: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024
    ; HSAPAL: S_ENDPGM 0, implicit [[S_MOV_B32_]]
    ; MESA-LABEL: name: groupstaticsize_s
    ; MESA: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @llvm.amdgcn.groupstaticsize
    ; MESA: S_ENDPGM 0, implicit [[S_MOV_B32_]]
    %0:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.groupstaticsize)
    S_ENDPGM 0, implicit %0
...