test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---

name: ds_swizzle_0
legalized:       true
regBankSelected: true
tracksRegLiveness: true


body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: ds_swizzle_0
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 0, 0, implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 0
    S_ENDPGM 0, implicit %1

...

---

name: ds_swizzle_65535
legalized:       true
regBankSelected: true
tracksRegLiveness: true


body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: ds_swizzle_65535
    ; CHECK: liveins: $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[DS_SWIZZLE_B32_:%[0-9]+]]:vgpr_32 = DS_SWIZZLE_B32 [[COPY]], 65535, 0, implicit $exec
    ; CHECK: S_ENDPGM 0, implicit [[DS_SWIZZLE_B32_]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ds.swizzle), %0, 65535
    S_ENDPGM 0, implicit %1

...