test/CodeGen/AMDGPU/GlobalISel/combine-urem-pow-2.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

---
name: urem_s32_var_const0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: urem_s32_var_const0
    ; GCN: liveins: $vgpr0
    ; GCN: %var:_(s32) = COPY $vgpr0
    ; GCN: %const:_(s32) = G_CONSTANT i32 0
    ; GCN: %rem:_(s32) = G_UREM %var, %const
    ; GCN: $vgpr0 = COPY %rem(s32)
    %var:_(s32) = COPY $vgpr0
    %const:_(s32) = G_CONSTANT i32 0
    %rem:_(s32) = G_UREM %var, %const
    $vgpr0 = COPY %rem
...

---
name: urem_s32_var_const1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: urem_s32_var_const1
    ; GCN: liveins: $vgpr0
    ; GCN: %const:_(s32) = G_CONSTANT i32 1
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %const, [[C]]
    ; GCN: $vgpr0 = COPY [[ADD]](s32)
    %var:_(s32) = COPY $vgpr0
    %const:_(s32) = G_CONSTANT i32 1
    %rem:_(s32) = G_UREM %var, %const
    $vgpr0 = COPY %rem
...

---
name: urem_s32_var_const2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0

    ; GCN-LABEL: name: urem_s32_var_const2
    ; GCN: liveins: $vgpr0
    ; GCN: %var:_(s32) = COPY $vgpr0
    ; GCN: %const:_(s32) = G_CONSTANT i32 2
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %const, [[C]]
    ; GCN: %rem:_(s32) = G_AND %var, [[ADD]]
    ; GCN: $vgpr0 = COPY %rem(s32)
    %var:_(s32) = COPY $vgpr0
    %const:_(s32) = G_CONSTANT i32 2
    %rem:_(s32) = G_UREM %var, %const
    $vgpr0 = COPY %rem
...

---
name: urem_s32_var_shl1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: urem_s32_var_shl1
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN: %var:_(s32) = COPY $vgpr0
    ; GCN: %shift_amt:_(s32) = COPY $vgpr1
    ; GCN: %one:_(s32) = G_CONSTANT i32 1
    ; GCN: %one_bit:_(s32) = G_SHL %one, %shift_amt(s32)
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %one_bit, [[C]]
    ; GCN: %rem:_(s32) = G_AND %var, [[ADD]]
    ; GCN: $vgpr0 = COPY %rem(s32)
    %var:_(s32) = COPY $vgpr0
    %shift_amt:_(s32) = COPY $vgpr1
    %one:_(s32) = G_CONSTANT i32 1
    %one_bit:_(s32) = G_SHL %one, %shift_amt
    %rem:_(s32) = G_UREM %var, %one_bit
    $vgpr0 = COPY %rem
...

---
name: urem_s64_var_shl1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2

    ; GCN-LABEL: name: urem_s64_var_shl1
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2
    ; GCN: %var:_(s64) = COPY $vgpr0_vgpr1
    ; GCN: %shiftamt:_(s32) = COPY $vgpr2
    ; GCN: %one:_(s64) = G_CONSTANT i64 1
    ; GCN: %one_bit:_(s64) = G_SHL %one, %shiftamt(s32)
    ; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
    ; GCN: [[ADD:%[0-9]+]]:_(s64) = G_ADD %one_bit, [[C]]
    ; GCN: %rem:_(s64) = G_AND %var, [[ADD]]
    ; GCN: $vgpr0_vgpr1 = COPY %rem(s64)
    %var:_(s64) = COPY $vgpr0_vgpr1
    %shiftamt:_(s32) = COPY $vgpr2
    %one:_(s64) = G_CONSTANT i64 1
    %one_bit:_(s64) = G_SHL %one, %shiftamt
    %rem:_(s64) = G_UREM %var, %one_bit
    $vgpr0_vgpr1 = COPY %rem
...

---
name: urem_v2s32_var_shl1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GCN-LABEL: name: urem_v2s32_var_shl1
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    ; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
    ; GCN: %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
    ; GCN: %one:_(s32) = G_CONSTANT i32 1
    ; GCN: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32)
    ; GCN: %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt(<2 x s32>)
    ; GCN: %rem:_(<2 x s32>) = G_UREM %var, %one_bit
    ; GCN: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
    %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
    %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
    %one:_(s32) = G_CONSTANT i32 1
    %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one
    %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt
    %rem:_(<2 x s32>) = G_UREM %var, %one_bit
    $vgpr0_vgpr1 = COPY %rem
...

---
name: urem_v2s16_var_const4_build_vector_trunc
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: urem_v2s16_var_const4_build_vector_trunc
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN: %var:_(<2 x s16>) = COPY $vgpr0
    ; GCN: %four:_(s32) = G_CONSTANT i32 4
    ; GCN: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %four(s32)
    ; GCN: %rem:_(<2 x s16>) = G_UREM %var, %four_vec
    ; GCN: $vgpr0 = COPY %rem(<2 x s16>)
    %var:_(<2 x s16>) = COPY $vgpr0
    %shift_amt:_(<2 x s16>) = COPY $vgpr1
    %four:_(s32) = G_CONSTANT i32 4
    %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %four
    %rem:_(<2 x s16>) = G_UREM %var, %four_vec
    $vgpr0 = COPY %rem
...