test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s

---
name:            ushlsat_and_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_and_1
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1073741820
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C1]], [[C]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %4:_(s32) = G_CONSTANT i32 1073741820
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %6:_(s32) = G_USHLSAT %5, %2(s32)
    $sgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_and_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_and_2
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870880
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 5
    %4:_(s32) = G_CONSTANT i32 536870880
    %6:_(s32) = G_CONSTANT i32 3
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_and_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_and_3
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 65536
    %6:_(s32) = G_CONSTANT i32 16
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_or_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_or_1
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073741821
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C1]], [[C]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %4:_(s32) = G_CONSTANT i32 -1073741821
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %6:_(s32) = G_USHLSAT %5, %2(s32)
    $sgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_or_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_or_2
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -536870881
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 5
    %4:_(s32) = G_CONSTANT i32 -536870881
    %6:_(s32) = G_CONSTANT i32 3
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_or_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_or_3
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 65536
    %6:_(s32) = G_CONSTANT i32 16
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            ushlsat_xor
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: ushlsat_xor
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 43690
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[USHLSAT]], [[USHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 43690
    %6:_(s32) = G_CONSTANT i32 5
    %3:_(s32) = G_USHLSAT %0, %2(s32)
    %5:_(s32) = G_XOR %3, %4
    %7:_(s32) = G_USHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_and_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_and_1
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1073741820
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C1]], [[C]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %4:_(s32) = G_CONSTANT i32 1073741820
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %6:_(s32) = G_SSHLSAT %5, %2(s32)
    $sgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_and_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_and_2
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 536870880
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 5
    %4:_(s32) = G_CONSTANT i32 536870880
    %6:_(s32) = G_CONSTANT i32 3
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_and_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_and_3
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[AND]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 65536
    %6:_(s32) = G_CONSTANT i32 16
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_AND %3, %4
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_or_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_or_1
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1073741821
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C1]], [[C]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 2
    %4:_(s32) = G_CONSTANT i32 -1073741821
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %6:_(s32) = G_SSHLSAT %5, %2(s32)
    $sgpr0 = COPY %6(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_or_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_or_2
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -536870881
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 5
    %4:_(s32) = G_CONSTANT i32 -536870881
    %6:_(s32) = G_CONSTANT i32 3
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_or_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_or_3
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 19
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[OR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 65536
    %6:_(s32) = G_CONSTANT i32 16
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_OR %3, %4
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...
---
name:            sshlsat_xor
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sshlsat_xor
    ; CHECK: liveins: $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 43690
    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; CHECK: [[SSHLSAT:%[0-9]+]]:_(s32) = G_SSHLSAT [[COPY]], [[C2]](s32)
    ; CHECK: [[SSHLSAT1:%[0-9]+]]:_(s32) = G_SSHLSAT [[C]], [[C1]](s32)
    ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[SSHLSAT]], [[SSHLSAT1]]
    ; CHECK: $sgpr0 = COPY [[XOR]](s32)
    ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_CONSTANT i32 3
    %4:_(s32) = G_CONSTANT i32 43690
    %6:_(s32) = G_CONSTANT i32 5
    %3:_(s32) = G_SSHLSAT %0, %2(s32)
    %5:_(s32) = G_XOR %3, %4
    %7:_(s32) = G_SSHLSAT %5, %6(s32)
    $sgpr0 = COPY %7(s32)
    SI_RETURN_TO_EPILOG implicit $sgpr0

...