test/CodeGen/AArch64/GlobalISel/legalize-reduce-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
---
name:            add_v16s8
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: add_v16s8
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load 16)
    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s8) = G_VECREDUCE_ADD [[LOAD]](<16 x s8>)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s8)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(<16 x s8>) = G_LOAD %0(p0) :: (load 16)
    %2:_(s8) = G_VECREDUCE_ADD %1(<16 x s8>)
    %3:_(s32) = G_ANYEXT %2(s8)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_v8s16
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: add_v8s16
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load 16)
    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s16) = G_VECREDUCE_ADD [[LOAD]](<8 x s16>)
    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[VECREDUCE_ADD]](s16)
    ; CHECK: $w0 = COPY [[ANYEXT]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(<8 x s16>) = G_LOAD %0(p0) :: (load 16)
    %2:_(s16) = G_VECREDUCE_ADD %1(<8 x s16>)
    %3:_(s32) = G_ANYEXT %2(s16)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_v4s32
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: add_v4s32
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load 16)
    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s32) = G_VECREDUCE_ADD [[LOAD]](<4 x s32>)
    ; CHECK: $w0 = COPY [[VECREDUCE_ADD]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(<4 x s32>) = G_LOAD %0(p0) :: (load 16)
    %2:_(s32) = G_VECREDUCE_ADD %1(<4 x s32>)
    $w0 = COPY %2(s32)
    RET_ReallyLR implicit $w0

...
---
name:            add_v2s64
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $x0

    ; CHECK-LABEL: name: add_v2s64
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load 16)
    ; CHECK: [[VECREDUCE_ADD:%[0-9]+]]:_(s64) = G_VECREDUCE_ADD [[LOAD]](<2 x s64>)
    ; CHECK: $x0 = COPY [[VECREDUCE_ADD]](s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %0:_(p0) = COPY $x0
    %1:_(<2 x s64>) = G_LOAD %0(p0) :: (load 16)
    %2:_(s64) = G_VECREDUCE_ADD %1(<2 x s64>)
    $x0 = COPY %2(s64)
    RET_ReallyLR implicit $x0

...