| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // Test host codegen. |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // Test target codegen - host bc file has to be created first. |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // Test target codegen - host bc file has to be created first. |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| |
| |
| |
| // We have 6 target regions |
| |
| |
| |
| // Check target registration is registered as a Ctor. |
| |
| |
| template<typename tx> |
| tx ftemplate(int n) { |
| tx a = 0; |
| |
| #pragma omp target parallel if(parallel: 0) |
| { |
| a += 1; |
| } |
| |
| short b = 1; |
| #pragma omp target parallel if(parallel: 1) |
| { |
| a += b; |
| } |
| |
| return a; |
| } |
| |
| static |
| int fstatic(int n) { |
| |
| #pragma omp target parallel if(n>1) |
| { |
| } |
| |
| #pragma omp target parallel if(target: n-2>2) |
| { |
| } |
| |
| return n+1; |
| } |
| |
| struct S1 { |
| double a; |
| |
| int r1(int n){ |
| int b = 1; |
| |
| #pragma omp target parallel if(parallel: n>3) |
| { |
| this->a = (double)b + 1.5; |
| } |
| |
| #pragma omp target parallel if(target: n>4) if(parallel: n>5) |
| { |
| this->a = 2.5; |
| } |
| |
| return (int)a; |
| } |
| }; |
| |
| int bar(int n){ |
| int a = 0; |
| |
| S1 S; |
| a += S.r1(n); |
| |
| a += fstatic(n); |
| |
| a += ftemplate<int>(n); |
| |
| return a; |
| } |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| // Check that the offloading functions are emitted and that the parallel function |
| // is appropriately guarded. |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| #endif |
| // CHECK1-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 |
| // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK1-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK1-NEXT: store double* [[A]], double** [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 |
| // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 |
| // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK1-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK1-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK1-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK1-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK1-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* |
| // CHECK1-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 |
| // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 |
| // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 |
| // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK1-NEXT: store double* [[A13]], double** [[TMP33]], align 8 |
| // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP34]], align 8 |
| // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 |
| // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 |
| // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 |
| // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK1-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK1-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK1-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK1-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK1: omp_offload.failed18: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK1: omp_offload.cont19: |
| // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.else: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 |
| // CHECK1-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK1-NEXT: ret i32 [[CONV21]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK1-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK1-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK1-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP8]], align 8 |
| // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK1-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK1-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK1-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.else: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK1: omp_if.then5: |
| // CHECK1-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK1-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK1: omp_offload.failed6: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK1: omp_offload.cont7: |
| // CHECK1-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK1: omp_if.else8: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_IF_END9]] |
| // CHECK1: omp_if.end9: |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK1-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK1-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK1-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK1: omp_offload.failed: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK1: omp_offload.cont: |
| // CHECK1-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 |
| // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* |
| // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 |
| // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 |
| // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] |
| // CHECK1: omp_offload.failed7: |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] |
| // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] |
| // CHECK1: omp_offload.cont8: |
| // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.else: |
| // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK1-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] |
| // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.else: |
| // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK1-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK1-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK1: omp_if.then: |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK1: omp_if.else: |
| // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK1-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: br label [[OMP_IF_END]] |
| // CHECK1: omp_if.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK1-SAME: () #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK1-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK1-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK1-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 |
| // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK2-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 |
| // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK2-NEXT: store double* [[A]], double** [[TMP8]], align 8 |
| // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 |
| // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 |
| // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 |
| // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 |
| // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 |
| // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 |
| // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK2-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK2: omp_offload.failed: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK2: omp_offload.cont: |
| // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK2-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK2-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK2-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK2-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* |
| // CHECK2-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 |
| // CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 |
| // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK2-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK2: omp_if.then: |
| // CHECK2-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 |
| // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK2-NEXT: store double* [[A13]], double** [[TMP33]], align 8 |
| // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP34]], align 8 |
| // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 |
| // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 |
| // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8 |
| // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK2-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK2-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK2-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK2-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK2: omp_offload.failed18: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK2: omp_offload.cont19: |
| // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK2: omp_if.else: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_IF_END]] |
| // CHECK2: omp_if.end: |
| // CHECK2-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 |
| // CHECK2-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK2-NEXT: ret i32 [[CONV21]] |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK2-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK2-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK2-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK2-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK2: omp_if.then: |
| // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 |
| // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 |
| // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP8]], align 8 |
| // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK2-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK2-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK2-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK2: omp_offload.failed: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK2: omp_offload.cont: |
| // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK2: omp_if.else: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_IF_END]] |
| // CHECK2: omp_if.end: |
| // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK2: omp_if.then5: |
| // CHECK2-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK2-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK2-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK2: omp_offload.failed6: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK2: omp_offload.cont7: |
| // CHECK2-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK2: omp_if.else8: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_IF_END9]] |
| // CHECK2: omp_if.end9: |
| // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK2-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK2-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK2-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 |
| // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 |
| // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 |
| // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK2: omp_offload.failed: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK2: omp_offload.cont: |
| // CHECK2-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 |
| // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 |
| // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 |
| // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 |
| // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8 |
| // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] |
| // CHECK2: omp_offload.failed7: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]] |
| // CHECK2: omp_offload.cont8: |
| // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK2-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK2: omp_if.then: |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK2: omp_if.else: |
| // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK2-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] |
| // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: br label [[OMP_IF_END]] |
| // CHECK2: omp_if.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK2: omp_if.then: |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK2: omp_if.else: |
| // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK2-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: br label [[OMP_IF_END]] |
| // CHECK2: omp_if.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK2-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK2-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK2: omp_if.then: |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK2: omp_if.else: |
| // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK2-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: br label [[OMP_IF_END]] |
| // CHECK2: omp_if.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK2-SAME: () #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK2-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK2-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK2-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 |
| // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK3-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK3-NEXT: store double* [[A]], double** [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK3-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK3-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK3-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK3-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK3-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* |
| // CHECK3-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 |
| // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 |
| // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK3-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK3: omp_if.then: |
| // CHECK3-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 |
| // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK3-NEXT: store double* [[A12]], double** [[TMP33]], align 4 |
| // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP34]], align 4 |
| // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 |
| // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 |
| // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4 |
| // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK3-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK3-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK3-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK3-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] |
| // CHECK3: omp_offload.failed17: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] |
| // CHECK3: omp_offload.cont18: |
| // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK3: omp_if.else: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_IF_END]] |
| // CHECK3: omp_if.end: |
| // CHECK3-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 |
| // CHECK3-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK3-NEXT: ret i32 [[CONV20]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK3-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK3-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK3-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK3-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK3: omp_if.then: |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP8]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK3-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK3-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK3-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK3: omp_if.else: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_IF_END]] |
| // CHECK3: omp_if.end: |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK3: omp_if.then5: |
| // CHECK3-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK3-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK3: omp_offload.failed6: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK3: omp_offload.cont7: |
| // CHECK3-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK3: omp_if.else8: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_IF_END9]] |
| // CHECK3: omp_if.end9: |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK3-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK3-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK3-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP6]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK3-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK3-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP24]], align 4 |
| // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK3: omp_offload.failed5: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK3: omp_offload.cont6: |
| // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK3-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK3: omp_if.then: |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK3: omp_if.else: |
| // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK3-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] |
| // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: br label [[OMP_IF_END]] |
| // CHECK3: omp_if.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK3: omp_if.then: |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK3: omp_if.else: |
| // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK3-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: br label [[OMP_IF_END]] |
| // CHECK3: omp_if.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK3-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK3-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK3: omp_if.then: |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK3: omp_if.else: |
| // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK3-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: br label [[OMP_IF_END]] |
| // CHECK3: omp_if.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK3-SAME: () #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK3-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK3-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK4-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK4-NEXT: store double* [[A]], double** [[TMP8]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 |
| // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 |
| // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 |
| // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK4-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK4: omp_offload.failed: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK4: omp_offload.cont: |
| // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK4-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK4-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK4-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK4-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* |
| // CHECK4-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 |
| // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 |
| // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 |
| // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK4-NEXT: store double* [[A12]], double** [[TMP33]], align 4 |
| // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP34]], align 4 |
| // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 |
| // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 |
| // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4 |
| // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK4-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK4-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK4-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK4-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] |
| // CHECK4: omp_offload.failed17: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT18]] |
| // CHECK4: omp_offload.cont18: |
| // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.else: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 |
| // CHECK4-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK4-NEXT: ret i32 [[CONV20]] |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK4-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK4-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK4-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK4-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP8]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK4-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK4-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK4-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK4-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK4: omp_offload.failed: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK4: omp_offload.cont: |
| // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.else: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK4-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK4: omp_if.then5: |
| // CHECK4-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK4-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK4-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK4: omp_offload.failed6: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK4: omp_offload.cont7: |
| // CHECK4-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK4: omp_if.else8: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_IF_END9]] |
| // CHECK4: omp_if.end9: |
| // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK4-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK4-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK4-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP6]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK4-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK4: omp_offload.failed: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK4: omp_offload.cont: |
| // CHECK4-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK4-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 |
| // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 |
| // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP24]], align 4 |
| // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK4: omp_offload.failed5: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK4: omp_offload.cont6: |
| // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK4-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.else: |
| // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK4-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] |
| // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.else: |
| // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK4-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK4-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK4-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK4: omp_if.then: |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK4: omp_if.else: |
| // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK4-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: br label [[OMP_IF_END]] |
| // CHECK4: omp_if.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK4-SAME: () #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK4-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK4-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK9: omp_if.then: |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK9: omp_if.else: |
| // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK9-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: br label [[OMP_IF_END]] |
| // CHECK9: omp_if.end: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK9-SAME: () #[[ATTR0]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK9: omp_if.then: |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK9: omp_if.else: |
| // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK9-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] |
| // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: br label [[OMP_IF_END]] |
| // CHECK9: omp_if.end: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK9-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK9-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK9: omp_if.then: |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK9-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK9: omp_if.else: |
| // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK9-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: br label [[OMP_IF_END]] |
| // CHECK9: omp_if.end: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK9-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK9-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK9-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] |
| // CHECK9-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK10: omp_if.then: |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK10: omp_if.else: |
| // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK10-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: br label [[OMP_IF_END]] |
| // CHECK10: omp_if.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK10-SAME: () #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK10: omp_if.then: |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK10: omp_if.else: |
| // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK10-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] |
| // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: br label [[OMP_IF_END]] |
| // CHECK10: omp_if.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK10-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK10-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK10: omp_if.then: |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK10-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK10: omp_if.else: |
| // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK10-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: br label [[OMP_IF_END]] |
| // CHECK10: omp_if.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK10-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK10-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] |
| // CHECK10-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK11: omp_if.then: |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK11: omp_if.else: |
| // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK11-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: br label [[OMP_IF_END]] |
| // CHECK11: omp_if.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK11-SAME: () #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK11: omp_if.then: |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK11: omp_if.else: |
| // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK11-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] |
| // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: br label [[OMP_IF_END]] |
| // CHECK11: omp_if.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK11-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK11-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK11: omp_if.then: |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK11-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK11: omp_if.else: |
| // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK11-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: br label [[OMP_IF_END]] |
| // CHECK11: omp_if.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK11-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK11-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] |
| // CHECK11-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK12: omp_if.then: |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK12: omp_if.else: |
| // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK12-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: br label [[OMP_IF_END]] |
| // CHECK12: omp_if.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK12-SAME: () #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK12: omp_if.then: |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK12: omp_if.else: |
| // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK12-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] |
| // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: br label [[OMP_IF_END]] |
| // CHECK12: omp_if.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK12-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK12-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK12: omp_if.then: |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK12-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK12: omp_if.else: |
| // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK12-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: br label [[OMP_IF_END]] |
| // CHECK12: omp_if.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK12-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] |
| // CHECK12-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 |
| // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) |
| // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK17-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK17-NEXT: store double* [[A]], double** [[TMP8]], align 8 |
| // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 |
| // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 |
| // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 |
| // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 |
| // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 |
| // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 |
| // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK17-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK17: omp_offload.failed: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK17: omp_offload.cont: |
| // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK17-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK17-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK17-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK17-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* |
| // CHECK17-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 |
| // CHECK17-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 |
| // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK17-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK17: omp_if.then: |
| // CHECK17-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 |
| // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK17-NEXT: store double* [[A13]], double** [[TMP33]], align 8 |
| // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP34]], align 8 |
| // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 |
| // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 |
| // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 |
| // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK17-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK17-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK17-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK17-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK17: omp_offload.failed18: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK17: omp_offload.cont19: |
| // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK17: omp_if.else: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_IF_END]] |
| // CHECK17: omp_if.end: |
| // CHECK17-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 |
| // CHECK17-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK17-NEXT: ret i32 [[CONV21]] |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK17-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK17-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK17-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK17-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK17: omp_if.then: |
| // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 |
| // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 |
| // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP8]], align 8 |
| // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK17-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK17-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK17-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK17: omp_offload.failed: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK17: omp_offload.cont: |
| // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK17: omp_if.else: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_IF_END]] |
| // CHECK17: omp_if.end: |
| // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK17-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK17: omp_if.then5: |
| // CHECK17-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK17-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK17: omp_offload.failed6: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK17: omp_offload.cont7: |
| // CHECK17-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK17: omp_if.else8: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_IF_END9]] |
| // CHECK17: omp_if.end9: |
| // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK17-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK17-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 |
| // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 |
| // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 |
| // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK17: omp_offload.failed: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK17: omp_offload.cont: |
| // CHECK17-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 |
| // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 |
| // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 |
| // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 |
| // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 |
| // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 |
| // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 |
| // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* |
| // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 |
| // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 |
| // CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 |
| // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] |
| // CHECK17: omp_offload.failed7: |
| // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] |
| // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] |
| // CHECK17: omp_offload.cont8: |
| // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK17-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK17: omp_if.then: |
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK17: omp_if.else: |
| // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK17-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] |
| // CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: br label [[OMP_IF_END]] |
| // CHECK17: omp_if.end: |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK17: omp_if.then: |
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK17: omp_if.else: |
| // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK17-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: br label [[OMP_IF_END]] |
| // CHECK17: omp_if.end: |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK17-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK17: omp_if.then: |
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK17: omp_if.else: |
| // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK17-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: br label [[OMP_IF_END]] |
| // CHECK17: omp_if.end: |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK17-SAME: () #[[ATTR1]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK17-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK17-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK17-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK17-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK17-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK17-NEXT: entry: |
| // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK17-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 |
| // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) |
| // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) |
| // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK18-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 |
| // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8 |
| // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK18-NEXT: store double* [[A]], double** [[TMP8]], align 8 |
| // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 |
| // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP11]], align 8 |
| // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP13]], align 8 |
| // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 |
| // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP16]], align 8 |
| // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP18]], align 8 |
| // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK18-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK18: omp_offload.failed: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK18: omp_offload.cont: |
| // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK18-NEXT: [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK18-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK18-NEXT: [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK18-NEXT: [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8* |
| // CHECK18-NEXT: [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1 |
| // CHECK18-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8 |
| // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK18-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK18: omp_if.then: |
| // CHECK18-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8 |
| // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK18-NEXT: store double* [[A13]], double** [[TMP33]], align 8 |
| // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP34]], align 8 |
| // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP36]], align 8 |
| // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP28]], i64* [[TMP38]], align 8 |
| // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 |
| // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1 |
| // CHECK18-NEXT: [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK18-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK18-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK18-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK18: omp_offload.failed18: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK18: omp_offload.cont19: |
| // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK18: omp_if.else: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_IF_END]] |
| // CHECK18: omp_if.end: |
| // CHECK18-NEXT: [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP46:%.*]] = load double, double* [[A20]], align 8 |
| // CHECK18-NEXT: [[CONV21:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK18-NEXT: ret i32 [[CONV21]] |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK18-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK18-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK18-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK18-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK18: omp_if.then: |
| // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP5]], align 8 |
| // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP7]], align 8 |
| // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP8]], align 8 |
| // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK18-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK18-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK18-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK18-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK18: omp_offload.failed: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK18: omp_offload.cont: |
| // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK18: omp_if.else: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_IF_END]] |
| // CHECK18: omp_if.end: |
| // CHECK18-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK18-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK18-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK18: omp_if.then5: |
| // CHECK18-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK18-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK18-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK18: omp_offload.failed6: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK18: omp_offload.cont7: |
| // CHECK18-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK18: omp_if.else8: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_IF_END9]] |
| // CHECK18: omp_if.end9: |
| // CHECK18-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK18-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 |
| // CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK18-NEXT: [[A_CASTED1:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8 |
| // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 |
| // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 |
| // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 |
| // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK18: omp_offload.failed: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK18: omp_offload.cont: |
| // CHECK18-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV2]], align 4 |
| // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8 |
| // CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV3]], align 2 |
| // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP16]], align 8 |
| // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP18]], align 8 |
| // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 |
| // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP21]], align 8 |
| // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1 |
| // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* |
| // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP23]], align 8 |
| // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1 |
| // CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 |
| // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 |
| // CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] |
| // CHECK18: omp_offload.failed7: |
| // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR3]] |
| // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] |
| // CHECK18: omp_offload.cont8: |
| // CHECK18-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK18-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK18: omp_if.then: |
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK18: omp_if.else: |
| // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK18-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR3]] |
| // CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: br label [[OMP_IF_END]] |
| // CHECK18: omp_if.end: |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK18: omp_if.then: |
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK18: omp_if.else: |
| // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK18-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: br label [[OMP_IF_END]] |
| // CHECK18: omp_if.end: |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK18-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK18-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK18: omp_if.then: |
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK18: omp_if.else: |
| // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK18-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: br label [[OMP_IF_END]] |
| // CHECK18: omp_if.end: |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK18-SAME: () #[[ATTR1]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK18-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK18-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK18-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR3]] |
| // CHECK18-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK18-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK18-NEXT: entry: |
| // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK18-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 |
| // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) |
| // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK19-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 |
| // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK19-NEXT: store double* [[A]], double** [[TMP8]], align 4 |
| // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 |
| // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 |
| // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 |
| // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 |
| // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 |
| // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 |
| // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK19-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK19: omp_offload.failed: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK19: omp_offload.cont: |
| // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK19-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK19-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK19-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK19-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* |
| // CHECK19-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 |
| // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 |
| // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK19: omp_if.then: |
| // CHECK19-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 |
| // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK19-NEXT: store double* [[A12]], double** [[TMP33]], align 4 |
| // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP34]], align 4 |
| // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 |
| // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 |
| // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 |
| // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK19-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK19-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK19-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK19-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] |
| // CHECK19: omp_offload.failed17: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT18]] |
| // CHECK19: omp_offload.cont18: |
| // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK19: omp_if.else: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_IF_END]] |
| // CHECK19: omp_if.end: |
| // CHECK19-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 |
| // CHECK19-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK19-NEXT: ret i32 [[CONV20]] |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK19-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK19-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK19-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK19-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK19: omp_if.then: |
| // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 |
| // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 |
| // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP8]], align 4 |
| // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK19-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK19-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK19-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK19: omp_offload.failed: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK19: omp_offload.cont: |
| // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK19: omp_if.else: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_IF_END]] |
| // CHECK19: omp_if.end: |
| // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK19-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK19: omp_if.then5: |
| // CHECK19-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK19-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK19: omp_offload.failed6: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK19: omp_offload.cont7: |
| // CHECK19-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK19: omp_if.else8: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_IF_END9]] |
| // CHECK19: omp_if.end9: |
| // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK19-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK19-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 |
| // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP6]], align 4 |
| // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK19-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK19: omp_offload.failed: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK19: omp_offload.cont: |
| // CHECK19-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 |
| // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 |
| // CHECK19-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK19-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 |
| // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 |
| // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 |
| // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 |
| // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 |
| // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* |
| // CHECK19-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 |
| // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 |
| // CHECK19-NEXT: store i8* null, i8** [[TMP24]], align 4 |
| // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK19: omp_offload.failed5: |
| // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] |
| // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK19: omp_offload.cont6: |
| // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK19-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK19: omp_if.then: |
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK19: omp_if.else: |
| // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK19-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] |
| // CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: br label [[OMP_IF_END]] |
| // CHECK19: omp_if.end: |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK19: omp_if.then: |
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK19: omp_if.else: |
| // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK19-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: br label [[OMP_IF_END]] |
| // CHECK19: omp_if.end: |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK19-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK19: omp_if.then: |
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK19: omp_if.else: |
| // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK19-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: br label [[OMP_IF_END]] |
| // CHECK19: omp_if.end: |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK19-SAME: () #[[ATTR1]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK19-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK19-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK19-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK19-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK19-NEXT: entry: |
| // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK19-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@_Z3bari |
| // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 |
| // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] |
| // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) |
| // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] |
| // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 |
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) |
| // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] |
| // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 |
| // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: ret i32 [[TMP6]] |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei |
| // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 1, i32* [[B]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 |
| // CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP1]], i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK20-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 |
| // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1** |
| // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4 |
| // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double** |
| // CHECK20-NEXT: store double* [[A]], double** [[TMP8]], align 4 |
| // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 |
| // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP11]], align 4 |
| // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP13]], align 4 |
| // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 |
| // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP16]], align 4 |
| // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP18]], align 4 |
| // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1 |
| // CHECK20-NEXT: [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) |
| // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 |
| // CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK20: omp_offload.failed: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR3:[0-9]+]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK20: omp_offload.cont: |
| // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5 |
| // CHECK20-NEXT: [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK20-NEXT: [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK20-NEXT: [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1 |
| // CHECK20-NEXT: [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8* |
| // CHECK20-NEXT: [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1 |
| // CHECK20-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4 |
| // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4 |
| // CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK20: omp_if.then: |
| // CHECK20-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1** |
| // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4 |
| // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double** |
| // CHECK20-NEXT: store double* [[A12]], double** [[TMP33]], align 4 |
| // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP34]], align 4 |
| // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP36]], align 4 |
| // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP28]], i32* [[TMP38]], align 4 |
| // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 |
| // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1 |
| // CHECK20-NEXT: [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1 |
| // CHECK20-NEXT: [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]]) |
| // CHECK20-NEXT: [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0 |
| // CHECK20-NEXT: br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] |
| // CHECK20: omp_offload.failed17: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT18]] |
| // CHECK20: omp_offload.cont18: |
| // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK20: omp_if.else: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_IF_END]] |
| // CHECK20: omp_if.end: |
| // CHECK20-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP46:%.*]] = load double, double* [[A19]], align 4 |
| // CHECK20-NEXT: [[CONV20:%.*]] = fptosi double [[TMP46]] to i32 |
| // CHECK20-NEXT: ret i32 [[CONV20]] |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici |
| // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1 |
| // CHECK20-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* |
| // CHECK20-NEXT: [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8 |
| // CHECK20-NEXT: store i8 [[FROMBOOL1]], i8* [[CONV]], align 1 |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1 |
| // CHECK20-NEXT: br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK20: omp_if.then: |
| // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP5]], align 4 |
| // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 |
| // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP8]], align 4 |
| // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 |
| // CHECK20-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1 |
| // CHECK20-NEXT: [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]]) |
| // CHECK20-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 |
| // CHECK20-NEXT: br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK20: omp_offload.failed: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK20: omp_offload.cont: |
| // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK20: omp_if.else: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_IF_END]] |
| // CHECK20: omp_if.end: |
| // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2 |
| // CHECK20-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2 |
| // CHECK20-NEXT: br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]] |
| // CHECK20: omp_if.then5: |
| // CHECK20-NEXT: [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) |
| // CHECK20-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 |
| // CHECK20-NEXT: br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] |
| // CHECK20: omp_offload.failed6: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] |
| // CHECK20: omp_offload.cont7: |
| // CHECK20-NEXT: br label [[OMP_IF_END9:%.*]] |
| // CHECK20: omp_if.else8: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_IF_END9]] |
| // CHECK20: omp_if.end9: |
| // CHECK20-NEXT: [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], 1 |
| // CHECK20-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i |
| // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 |
| // CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 |
| // CHECK20-NEXT: [[A_CASTED1:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4 |
| // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP3]], align 4 |
| // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 |
| // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP6]], align 4 |
| // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1) |
| // CHECK20-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 |
| // CHECK20-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK20: omp_offload.failed: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK20: omp_offload.cont: |
| // CHECK20-NEXT: store i16 1, i16* [[B]], align 2 |
| // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP11]], i32* [[A_CASTED1]], align 4 |
| // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4 |
| // CHECK20-NEXT: [[TMP13:%.*]] = load i16, i16* [[B]], align 2 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK20-NEXT: store i16 [[TMP13]], i16* [[CONV]], align 2 |
| // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 |
| // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 |
| // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 |
| // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP21]], align 4 |
| // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1 |
| // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* |
| // CHECK20-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 |
| // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1 |
| // CHECK20-NEXT: store i8* null, i8** [[TMP24]], align 4 |
| // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0 |
| // CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) |
| // CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 |
| // CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]] |
| // CHECK20: omp_offload.failed5: |
| // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR3]] |
| // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT6]] |
| // CHECK20: omp_offload.cont6: |
| // CHECK20-NEXT: [[TMP29:%.*]] = load i32, i32* [[A]], align 4 |
| // CHECK20-NEXT: ret i32 [[TMP29]] |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK20: omp_if.then: |
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK20: omp_if.else: |
| // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK20-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR3]] |
| // CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: br label [[OMP_IF_END]] |
| // CHECK20: omp_if.end: |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK20: omp_if.then: |
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK20: omp_if.else: |
| // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK20-NEXT: call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR3]] |
| // CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: br label [[OMP_IF_END]] |
| // CHECK20: omp_if.end: |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR2]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK20-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK20-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK20: omp_if.then: |
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) |
| // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK20: omp_if.else: |
| // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK20-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR3]] |
| // CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: br label [[OMP_IF_END]] |
| // CHECK20: omp_if.end: |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK20-SAME: () #[[ATTR1]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK20-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK20-NEXT: call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR3]] |
| // CHECK20-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8 |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 |
| // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR2]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK20-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK20-NEXT: entry: |
| // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK20-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK25-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK25: omp_if.then: |
| // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK25-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK25: omp_if.else: |
| // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK25-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: br label [[OMP_IF_END]] |
| // CHECK25: omp_if.end: |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK25-SAME: () #[[ATTR0]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK25-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK25-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK25: omp_if.then: |
| // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK25-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK25: omp_if.else: |
| // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK25-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] |
| // CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: br label [[OMP_IF_END]] |
| // CHECK25: omp_if.end: |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK25-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK25-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK25-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK25: omp_if.then: |
| // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK25-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK25: omp_if.else: |
| // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK25-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: br label [[OMP_IF_END]] |
| // CHECK25: omp_if.end: |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK25-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK25-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK25-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK25-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] |
| // CHECK25-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK25-NEXT: entry: |
| // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK25-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK26-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK26: omp_if.then: |
| // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK26-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK26: omp_if.else: |
| // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK26-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: br label [[OMP_IF_END]] |
| // CHECK26: omp_if.end: |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK26-SAME: () #[[ATTR0]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* |
| // CHECK26-NEXT: store i32 [[TMP2]], i32* [[CONV2]], align 4 |
| // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK26-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8 |
| // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK26: omp_if.then: |
| // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]]) |
| // CHECK26-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK26: omp_if.else: |
| // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK26-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]] |
| // CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: br label [[OMP_IF_END]] |
| // CHECK26: omp_if.end: |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* |
| // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 |
| // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK26-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8 |
| // CHECK26-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK26-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK26: omp_if.then: |
| // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK26-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK26: omp_if.else: |
| // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK26-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: br label [[OMP_IF_END]] |
| // CHECK26: omp_if.end: |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 |
| // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK26-SAME: (i64 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK26-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK26-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK26-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]] |
| // CHECK26-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* |
| // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 |
| // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 |
| // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16* |
| // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 |
| // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 |
| // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK26-NEXT: entry: |
| // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 |
| // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 |
| // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* |
| // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* |
| // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 |
| // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] |
| // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 |
| // CHECK26-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK27-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK27: omp_if.then: |
| // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK27-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK27: omp_if.else: |
| // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK27-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: br label [[OMP_IF_END]] |
| // CHECK27: omp_if.end: |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK27-SAME: () #[[ATTR0]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK27-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK27: omp_if.then: |
| // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK27-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK27: omp_if.else: |
| // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK27-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] |
| // CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: br label [[OMP_IF_END]] |
| // CHECK27: omp_if.end: |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK27-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK27-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK27-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK27: omp_if.then: |
| // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK27-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK27: omp_if.else: |
| // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK27-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: br label [[OMP_IF_END]] |
| // CHECK27: omp_if.end: |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK27-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK27-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK27-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK27-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] |
| // CHECK27-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK27-NEXT: entry: |
| // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK27-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 |
| // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) |
| // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK28-NEXT: [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1 |
| // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK28: omp_if.then: |
| // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) |
| // CHECK28-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK28: omp_if.else: |
| // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK28-NEXT: call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2:[0-9]+]] |
| // CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: br label [[OMP_IF_END]] |
| // CHECK28: omp_if.end: |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 |
| // CHECK28-SAME: () #[[ATTR0]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 |
| // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 |
| // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK28-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 |
| // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK28: omp_if.then: |
| // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]]) |
| // CHECK28-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK28: omp_if.else: |
| // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK28-NEXT: call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]] |
| // CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: br label [[OMP_IF_END]] |
| // CHECK28: omp_if.end: |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double |
| // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 |
| // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 |
| // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* |
| // CHECK28-NEXT: [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4 |
| // CHECK28-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1 |
| // CHECK28-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] |
| // CHECK28: omp_if.then: |
| // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) |
| // CHECK28-NEXT: br label [[OMP_IF_END:%.*]] |
| // CHECK28: omp_if.else: |
| // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK28-NEXT: call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]] |
| // CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: br label [[OMP_IF_END]] |
| // CHECK28: omp_if.end: |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 |
| // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 |
| // CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87 |
| // CHECK28-SAME: (i32 [[A:%.*]]) #[[ATTR0]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) |
| // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 |
| // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK28-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 |
| // CHECK28-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 |
| // CHECK28-NEXT: call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]] |
| // CHECK28-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 |
| // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 |
| // CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 |
| // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16* |
| // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 |
| // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 |
| // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) |
| // CHECK28-NEXT: ret void |
| // |
| // |
| // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 |
| // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { |
| // CHECK28-NEXT: entry: |
| // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 |
| // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* |
| // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 |
| // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 |
| // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] |
| // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 |
| // CHECK28-NEXT: ret void |
| // |
