| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // REQUIRES: aarch64-registered-target |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK |
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -o /dev/null %s |
| #include <arm_sve.h> |
| |
| #ifdef SVE_OVERLOADED_FORMS |
| // A simple used,unused... macro, long enough to represent any SVE builtin. |
| #define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 |
| #else |
| #define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 |
| #endif |
| |
| // CHECK-LABEL: @test_svzip1_s8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z14test_svzip1_s8u10__SVInt8_tu10__SVInt8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] |
| // |
| svint8_t test_svzip1_s8(svint8_t op1, svint8_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_s8,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_s16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_s16u11__SVInt16_tu11__SVInt16_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] |
| // |
| svint16_t test_svzip1_s16(svint16_t op1, svint16_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_s16,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_s32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_s32u11__SVInt32_tu11__SVInt32_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] |
| // |
| svint32_t test_svzip1_s32(svint32_t op1, svint32_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_s32,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_s64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_s64u11__SVInt64_tu11__SVInt64_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] |
| // |
| svint64_t test_svzip1_s64(svint64_t op1, svint64_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_s64,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_u8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z14test_svzip1_u8u11__SVUint8_tu11__SVUint8_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.aarch64.sve.zip1.nxv16i8(<vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]] |
| // |
| svuint8_t test_svzip1_u8(svuint8_t op1, svuint8_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_u8,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_u16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_u16u12__SVUint16_tu12__SVUint16_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i16> @llvm.aarch64.sve.zip1.nxv8i16(<vscale x 8 x i16> [[OP1:%.*]], <vscale x 8 x i16> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]] |
| // |
| svuint16_t test_svzip1_u16(svuint16_t op1, svuint16_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_u16,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_u32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_u32u12__SVUint32_tu12__SVUint32_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.zip1.nxv4i32(<vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]] |
| // |
| svuint32_t test_svzip1_u32(svuint32_t op1, svuint32_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_u32,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_u64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_u64u12__SVUint64_tu12__SVUint64_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i64> @llvm.aarch64.sve.zip1.nxv2i64(<vscale x 2 x i64> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]] |
| // |
| svuint64_t test_svzip1_u64(svuint64_t op1, svuint64_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_u64,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_f16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_f16u13__SVFloat16_tu13__SVFloat16_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.zip1.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]] |
| // |
| svfloat16_t test_svzip1_f16(svfloat16_t op1, svfloat16_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_f16,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_f32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_f32u13__SVFloat32_tu13__SVFloat32_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.zip1.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]] |
| // |
| svfloat32_t test_svzip1_f32(svfloat32_t op1, svfloat32_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_f32,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_f64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_f64u13__SVFloat64_tu13__SVFloat64_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.zip1.nxv2f64(<vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]] |
| // |
| svfloat64_t test_svzip1_f64(svfloat64_t op1, svfloat64_t op2) |
| { |
| return SVE_ACLE_FUNC(svzip1,_f64,,)(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_b8( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]) |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]] |
| // |
| // CPP-CHECK-LABEL: @_Z14test_svzip1_b8u10__SVBool_tu10__SVBool_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.zip1.nxv16i1(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]] |
| // |
| svbool_t test_svzip1_b8(svbool_t op1, svbool_t op2) |
| { |
| return svzip1_b8(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_b16( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.zip1.nxv8i1(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i1> [[TMP1]]) |
| // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP2]]) |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_b16u10__SVBool_tu10__SVBool_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.zip1.nxv8i1(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i1> [[TMP1]]) |
| // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP2]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| svbool_t test_svzip1_b16(svbool_t op1, svbool_t op2) |
| { |
| return svzip1_b16(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_b32( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.zip1.nxv4i1(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i1> [[TMP1]]) |
| // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP2]]) |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_b32u10__SVBool_tu10__SVBool_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.zip1.nxv4i1(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i1> [[TMP1]]) |
| // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP2]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| svbool_t test_svzip1_b32(svbool_t op1, svbool_t op2) |
| { |
| return svzip1_b32(op1, op2); |
| } |
| |
| // CHECK-LABEL: @test_svzip1_b64( |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.zip1.nxv2i1(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP1]]) |
| // CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP2]]) |
| // CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| // CPP-CHECK-LABEL: @_Z15test_svzip1_b64u10__SVBool_tu10__SVBool_t( |
| // CPP-CHECK-NEXT: entry: |
| // CPP-CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[OP1:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[OP2:%.*]]) |
| // CPP-CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.zip1.nxv2i1(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP1]]) |
| // CPP-CHECK-NEXT: [[TMP3:%.*]] = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP2]]) |
| // CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP3]] |
| // |
| svbool_t test_svzip1_b64(svbool_t op1, svbool_t op2) |
| { |
| return svzip1_b64(op1, op2); |
| } |
