[RISCV][Clang] Drop the assembly tests for RVV intrinsics.
We had verified the correctness of all intrinsics in downstream, so
dropping the assembly tests to decrease the check-clang time.
It would remove 1/3 of the RUN lines.
https://reviews.llvm.org/D99151#2654154 mentions why we need to have
the ASM tests before.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D100617
GitOrigin-RevId: ca9e52f67cb337167f9cc37fe3f81bc38383b8df
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
index 1790288..bfed7a1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vaadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vaadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
index 8e6c592..f684ce2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vadc_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
index fc783e7..2834874 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
@@ -4,10 +4,7 @@
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
index 1a3d0a0..12ade5d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vand_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
index ac62381..fc09310 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vasub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vasub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
index 3a412c0..a090359 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vdiv.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vdiv_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
index 25fc2fe..a51128d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfadd.c
@@ -4,10 +4,7 @@
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
index 77e9fee..1357980 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfclass.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfclass_v_u32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
index 640eebf..46d6844 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfcvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfcvt_x_f_v_i32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
index c38fdbe..ca2e4a45 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfdiv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfdiv_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
index 4cfa5df..3e620ec 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfirst.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfirst_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
index 130f599..e4c75c4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmacc_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
index fbc3a42..c480b2e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
index a77883f..7811ac3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmax.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmax_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
index d1c5a30..89bec79 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmerge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmerge_vfm_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
index c471c84..2d0c24c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmin.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmin_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
index ad19ae8..d99603e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmsac_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
index 91c393d..ac2698ba 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
index 2452311..7918ddd 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmul.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmul_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
index 02dda02..d0fac7a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfmv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmv_f_s_f32mf2_f32(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
index af9394f..b2d0780 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfncvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfncvt_x_f_w_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
index 816d4af..3a854a3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmacc_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
index 7bddabb..1d314fc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
index dbffecd..c9865da 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmsac_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
index ae28fcd..80dfbff 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfnmsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
index 46432da..56bbde1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrdiv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrdiv_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
index 4834049..4156695 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrec7.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrec7_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
index c852f99..f9ff3a6 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredmax_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
index daf7cd7..87206f8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredmin_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
index 5d03271..2d931ef 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredsum_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
index d24dbd6..1543518 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsqrt7.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrsqrt7_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
index 9a69688..6105e2d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfrsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrsub_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
index 296d97f..5686f4a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsgnj.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsgnj_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
index 60847f4..65687a3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1down.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
index 81e8d33..aa462de 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfslide1up.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
index 6d330b4..e6ec7dc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsqrt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsqrt_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
index 591e260..78eeca2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
index e62526b..002a922 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwadd_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
index 95ee810..9c4f599 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwcvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
index 15e79f5..eca89a5 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmacc_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
index e2148c9..ccb70d8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmsac_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
index c10067c..f625969 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwmul.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmul_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
index aa13e27..1a4d9e4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwnmacc_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
index 539f7d6..cdffa9f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwnmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwnmsac_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
index e1339bf..87c5092 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwredsum_vs_f32mf2_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
index d86264a..b4422bc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwsub_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
index 043924d..3f8dd05 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vid.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vid_v_u8mf8_m(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
index 653c8ac..7ed891a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/viota.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_viota_m_u8mf8_m(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
index 0b313a0..dd4f793 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vle.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vle8_v_i8mf8_m(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
index 5652eda..5229f2f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vloxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
index 75bb6bd..7f7075c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf8_m(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
index 15fa817..67f8084 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vluxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
index d8c9549..cd6e436 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmacc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmacc_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
index 41ac0b3..d34d31b 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmadc_vvm_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
index aea6899..2c17215 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
index 1d76256..e15ffbe 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmand_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
index 388fa93..27bda47 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmax.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmax_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
index e2c7873..4dd5777 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmerge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmerge_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
index ed73e9a..44b949d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfeq.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfeq_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
index 5d90b5e..b211fa0 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfge_vf_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
index 8a3d1da..1601d6b 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfgt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfgt_vf_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
index d0ea180..70785fe 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfle.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfle_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
index 4825bbb..56e8501 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmflt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmflt_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
index 4093ca0..4fbff2b 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmfne.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfne_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
index 6dd3e7a..8ed1b44 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmin.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmin_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c
index 7e0792e..419c5de 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnand_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c
index 7eed0c6..c542003 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c
index 9883130..c7f95fe 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c
index cc941bf..7302ed7 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsbc_vvm_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
index 03be5a6..baa09cf 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsbf_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
index c0729e5..78b2ee1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmseq.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmseq_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
index d98664e..46acc54 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsgt.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsgt_vx_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
index 0e6b39d..1beb5b5 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsif_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
index dcfce37..ed32bc3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsle.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsle_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
index 742d189..e5ae791 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmslt.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmslt_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
index 12d6e21..e6ee3c5 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsne.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsne_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
index f816cbc..d17e8da 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsof_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
index 0a370c7..1672798 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmul_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
index fff5ce3..41e4be0 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c
index ca5799c..abc44ea 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxnor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmxnor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c
index 809b4d8..3825212 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmxor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
index 450bd33..34b570a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnclip.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnclip_wv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
index 6771870..2867cde 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsac.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnmsac_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
index f71f384..4538f16 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnmsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnmsub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
index 1000376..d685cee 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnsra_wv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
index 9d17cfc..8506b89 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vnsrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnsrl_wv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
index 168a6f9..dfbc8a3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vor_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c
index 52f58be..6d94546 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vpopc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vpopc_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
index 17b893e..898fea1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredand_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
index e6b215d..80037b2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredmax_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
index cefff41..c3e87dc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredmin_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
index 034b7ef..66b8214 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredor_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
index 6fdadc8..2152b92 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredsum_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
index 3c9729a..523bb8c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredxor_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
index ff6e320..4a995e0 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrem.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrem_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
index 1e68480..9468041 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrgather.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
index 486232c..e91ae30 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vrsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrsub_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
index 2e1d8e8..64dc720 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
index e9f3b68..2ba1d42 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsbc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsbc_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
index b957f29..496cba2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vse8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
index 026fdbd..41201fb 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsext.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsext_vf2_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
index 744a45f..df3937f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1down.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
index 93c6ec6..97b15e7 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslide1up.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
index 6cb1239..3dbb7c2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslidedown.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
index 907cb04..1b667e2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vslideup.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
index e3fde37..88313c9 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsll.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsll_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
index ca0e02e..c13bd75 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsmul_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c
index 08c94ac..8e49b4c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsoxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
index 9b8a93e..e67201d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsra_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
index 46ad59c..55f0817 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsrl_vv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c
index b787820..da1a358 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
index c503159..e747232 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssra_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
index 35cec95..d8682a4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssrl_vv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
index 9e485c4..2cc75be 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vssub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
index 31e047d..88915c7 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c
index edcddfe..3177e89 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsuxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
index 744ea4d..5d6c231 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwadd_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
index c2a99cb..d872bfc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmacc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwmacc_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
index ea2e12f..5bc4250 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwmul_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
index ef6d793..2f04782 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwredsum_vs_i8mf8_i16m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
index 9c483f4..0779879 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwsub_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
index 42ba2e2..d4b7d06 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vxor_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
index 2dc9d3d..310fb57 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vzext.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vzext_vf2_u16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
index b7a9ee6..840cc2c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vaadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vaadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vadc.c b/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
index 01a4a6f..7499400 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vadc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vadc_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
index 902f5e0..567c7ab 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vadd.c
@@ -4,10 +4,7 @@
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vand.c b/test/CodeGen/RISCV/rvv-intrinsics/vand.c
index 33f2836..a2f895d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vand_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vasub.c b/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
index c7e376b..6bcf1a1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vasub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vasub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c b/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
index 3f2138a..1625819 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vdiv.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vdiv_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
index 43be374..5e9400a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfadd.c
@@ -4,10 +4,7 @@
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -target-feature +experimental-zfh -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c b/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
index 8068a02..374e453 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfclass.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfclass_v_u32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c b/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
index 87f0a97..b9bb920 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfcvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfcvt_x_f_v_i32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c b/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
index bca8b4c..cb1ec6f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfdiv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfdiv_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c b/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c
index e1201f2..61af88f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfirst.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfirst_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
index e0f83ff..e72571d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmacc_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
index 01ab843..a4d4121 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
index ee4cdb0..959f901 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmax.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmax_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
index be96573..0abe61e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmerge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmerge_vfm_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
index 2230af1..48d6552 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmin.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmin_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
index dcbab0c..50962a8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmsac_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
index 2c0e35c..84cac4d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
index 709f3e7..0432ac2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmul.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmul_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c b/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
index 4e7a44b..de59e7c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfmv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfmv_v_f_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c b/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
index 3f89ca5..2341c30 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfncvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfncvt_x_f_w_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
index 3040744..dfb2ec8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfnmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmacc_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
index 79cd39d..7143376 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfnmadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmadd_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
index 259e60f..2d11aef 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfnmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmsac_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
index a77ee03..546cb78 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfnmsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfnmsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c b/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
index e47ff2d..c8e643b 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfrdiv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrdiv_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c b/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
index a46874f..28bfb47 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfrec7.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrec7_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c b/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
index 13ab0a1..303d166 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredmax_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c b/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
index 6e4b0b1..8f3c7e4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredmin_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c b/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
index 190a6e3..a2948db 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfredsum_vs_f32mf2_f32m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c b/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
index 4866275..2c32137 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfrsqrt7.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrsqrt7_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
index d2a29ce..6f78c4c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfrsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfrsub_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c b/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
index a135be3..c021a38 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfsgnj.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsgnj_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c b/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
index d7a857f..229ff94 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfslide1down.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfslide1down_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c b/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
index 34d7cf3..ca9e707 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfslide1up.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfslide1up_vf_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c b/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
index f87c1e9..63dbdf8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfsqrt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsqrt_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
index dc8b198..074202d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfsub_vv_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
index 4f5ec65..c70e2a7 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwadd.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwadd_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
index ae01b1e..72c98cd 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwcvt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwcvt_f_x_v_f32mf2(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
index 0693c16..bebb0a6 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmacc_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
index cec278e..25b73b2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmsac_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
index b40af3e..5e5c782 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwmul.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwmul_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
index 4d15978..3bd472a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwnmacc.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwnmacc_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
index 44bd012..3de9cbb 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwnmsac.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwnmsac_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
index c010bcf..36dd4b9 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwredosum_vs_f32mf2_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
index 023ecd7..5431a2d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwredsum_vs_f32mf2_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
index 9d75dc9..b386d8d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vfwsub.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vfwsub_vv_f64m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vid.c b/test/CodeGen/RISCV/rvv-intrinsics/vid.c
index 314abf1..e856587 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vid.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vid.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vid_v_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/viota.c b/test/CodeGen/RISCV/rvv-intrinsics/viota.c
index dd7c7cd..9046eec 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/viota.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/viota.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_viota_m_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vle.c b/test/CodeGen/RISCV/rvv-intrinsics/vle.c
index ebbd552..3784ec5 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vle.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vle8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vleff.c b/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
index 58ab525..a23dc28 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vleff.c
@@ -6,12 +6,7 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s \
// RUN: -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f \
-// RUN: -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -S -o - %s >/dev/null 2>%t
-// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vle8ff_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c b/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
index 21ca49d..ebb69f1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S > /dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @testuxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vlse.c b/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
index f4d108d..1cea88c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vlse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vlse8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c b/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
index ae34fbe..0955f8c 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S > /dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @testuxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
index 44915ec..241df9f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmacc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmacc_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c b/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c
index 6204216..b9aedb3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmadc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmadc_vvm_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
index 8980828..c9e0478 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmand.c b/test/CodeGen/RISCV/rvv-intrinsics/vmand.c
index f89808d..6bece91 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmand_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmax.c b/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
index 11332ec..ee00964 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmax.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmax_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c b/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c
index 7042492..772bd92 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmclr.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmclr_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c b/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
index 72dbfa7..7240d44 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmerge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmerge_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c b/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
index 455cdb3..a87a08b 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmfeq.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfeq_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c b/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
index d252589..dfe7b61 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmfge.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfge_vf_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c b/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
index 12b3955..840a317 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmfgt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfgt_vf_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c b/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
index 8ae45a4..f04553e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmfle.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfle_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c b/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
index 7b87bd9..d1b83ba 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmflt.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmflt_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c b/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
index bbfe91c..92eb43e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmfne.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmfne_vv_f32mf2_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmin.c b/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
index 7af09cd..85f1884 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmin.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmin_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c b/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c
index c7fd8f5..05af7e9 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmnand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnand_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c b/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c
index 2641e55..996d1ed 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmnor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmnor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmor.c b/test/CodeGen/RISCV/rvv-intrinsics/vmor.c
index c6c6e7a..f423c72 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c
index 774de45..797ce31 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsbc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsbc_vvm_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
index df0afc9..28301ae 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsbf_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c b/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
index dd581dc..b3235ab 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmseq.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmseq_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmset.c b/test/CodeGen/RISCV/rvv-intrinsics/vmset.c
index bb61dfe..5957006 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmset.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmset.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmset_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
index 4fcac2a..fc8e61e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsgt.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsgt_vx_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
index f3ad1de..c145dd6 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsif_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
index 1959f49..bd4b03e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsle.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsle_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c b/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
index c872d30..c55b9ef 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmslt.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmslt_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
index 432c809..b24b911 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsne.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsne_vv_i8mf8_b64(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c b/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
index ccc66d4..617631d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmsof_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmul.c b/test/CodeGen/RISCV/rvv-intrinsics/vmul.c
index 165bd1a..ee5caa8 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmul_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmv.c b/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
index 1a779e2..c6f4237 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmv.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmv_v_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c b/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c
index 5f06b75..f3ba466 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmxnor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmxnor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c b/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c
index 9c84387..644a8b1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vmxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vmxor_mm_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c b/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c
index 5c3c0cb..b71b5b1 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vnclip.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnclip_wv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c b/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
index f3f2ee6..e8168dc 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vnmsac.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnmsac_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
index 4cc83f4..8106268 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vnmsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnmsub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c b/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c
index 5783d5e..ff2aad9 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vnsra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnsra_wv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c b/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c
index 38e4f10..a1ee09a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vnsrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vnsrl_wv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vor.c b/test/CodeGen/RISCV/rvv-intrinsics/vor.c
index 544b524..b5e8f7f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vor_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c b/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c
index a94aa34..74e7ae3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vpopc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vpopc_m_b1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredand.c b/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
index 268f2e4..f2d50d6 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredand.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredand_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c b/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
index 4901214..89a7e31 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredmax_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c b/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
index e9e8cac3..5595270 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredmin_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredor.c b/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
index c933e4a..f4ba6d6 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredor_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c b/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
index e574243..09d1936 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredsum_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c b/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
index 04de6d0..61aa929 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vredxor_vs_i8mf8_i8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vrem.c b/test/CodeGen/RISCV/rvv-intrinsics/vrem.c
index 06e0e8a..0ea2094 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vrem.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vrem.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrem_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c b/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
index 0268c4b..d4b8a04 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vrgather.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrgather_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c
index 51f9050..bf42d59 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vrsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vrsub_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c
index f81ebc0..6696cfd 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsadd_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c b/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
index b8f051b..aba0bb2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsbc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsbc_vvm_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vse.c b/test/CodeGen/RISCV/rvv-intrinsics/vse.c
index facd1aa..69d4e81 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vse8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c b/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c
index 5d68209..5b2b2e4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsetvl.c
@@ -4,10 +4,7 @@
// RUN: | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \
// RUN: | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsetvl_e8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c b/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c
index 447ca05..c4903a4 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsetvlmax.c
@@ -4,10 +4,7 @@
// RUN: | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -emit-llvm -o - %s \
// RUN: | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsetvlmax_e8m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsext.c b/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
index c263460..99a762f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsext.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsext_vf2_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c b/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c
index c35a3ff..1f8dfaf 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vslide1down.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslide1down_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c b/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c
index b1334da..540a023 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vslide1up.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslide1up_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c b/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
index 46d739e..c488065 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vslidedown.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslidedown_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c b/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
index 8c6b99e..13a3d55 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vslideup.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vslideup_vx_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsll.c b/test/CodeGen/RISCV/rvv-intrinsics/vsll.c
index be5add3..88249fe 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsll.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsll.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsll_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c b/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c
index e5d709a..58dea08 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsmul_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c b/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
index b9af7ca..9518221 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsoxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsoxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsra.c b/test/CodeGen/RISCV/rvv-intrinsics/vsra.c
index 4ad0bca..a3fe854 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsra_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c b/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c
index 9c5df42..4b0f6c3 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsrl_vv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsse.c b/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
index 851ba6f..96d96f2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsse.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsse8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vssra.c b/test/CodeGen/RISCV/rvv-intrinsics/vssra.c
index 717070e..70d7f24 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vssra.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vssra.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssra_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c b/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c
index 11b918b..f9a755d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vssrl.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssrl_vv_u8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vssub.c b/test/CodeGen/RISCV/rvv-intrinsics/vssub.c
index de2ae7a..1878143 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vssub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vssub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vssub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vsub.c
index 4ac644e..f348e9a 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsub_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c b/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
index 593cccb..a78799f 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vsuxei.c
@@ -4,10 +4,7 @@
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN: -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vsuxei8_v_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c b/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c
index 34071a7..d8f9d4d 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vwadd.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwadd_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c b/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
index caffdf7..45783f2 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vwmacc.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwmacc_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c b/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c
index 7d4a02f..b327c8e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vwmul.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwmul_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c b/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
index 3ccba3e..c767d82 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwredsum_vs_i8mf8_i16m1(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c b/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c
index dd29f72..ed6ca5e 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vwsub.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vwsub_vv_i16mf4(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vxor.c b/test/CodeGen/RISCV/rvv-intrinsics/vxor.c
index 2351c55..f256cbf 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vxor.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vxor.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vxor_vv_i8mf8(
diff --git a/test/CodeGen/RISCV/rvv-intrinsics/vzext.c b/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
index 5fd4609..d9ed460 100644
--- a/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
+++ b/test/CodeGen/RISCV/rvv-intrinsics/vzext.c
@@ -2,9 +2,7 @@
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +m -target-feature +experimental-v -Werror -Wall -o - %s -S >/dev/null 2>&1 | FileCheck --check-prefix=ASM --allow-empty %s
-// ASM-NOT: warning
#include <riscv_vector.h>
// CHECK-RV32-LABEL: @test_vzext_vf2_u16mf4(
