| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py |
| // REQUIRES: riscv-registered-target |
| // RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s |
| // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s |
| |
| #include <riscv_vector.h> |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b1( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b1( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmclr.nxv64i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] |
| // |
| vbool1_t test_vmclr_m_b1(size_t vl) { return vmclr_m_b1(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b2( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b2( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmclr.nxv32i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] |
| // |
| vbool2_t test_vmclr_m_b2(size_t vl) { return vmclr_m_b2(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b4( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b4( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmclr.nxv16i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] |
| // |
| vbool4_t test_vmclr_m_b4(size_t vl) { return vmclr_m_b4(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b8( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b8( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmclr.nxv8i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] |
| // |
| vbool8_t test_vmclr_m_b8(size_t vl) { return vmclr_m_b8(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b16( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b16( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmclr.nxv4i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] |
| // |
| vbool16_t test_vmclr_m_b16(size_t vl) { return vmclr_m_b16(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b32( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b32( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmclr.nxv2i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] |
| // |
| vbool32_t test_vmclr_m_b32(size_t vl) { return vmclr_m_b32(vl); } |
| |
| // CHECK-RV32-LABEL: @test_vmclr_m_b64( |
| // CHECK-RV32-NEXT: entry: |
| // CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i32(i32 [[VL:%.*]]) |
| // CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]] |
| // |
| // CHECK-RV64-LABEL: @test_vmclr_m_b64( |
| // CHECK-RV64-NEXT: entry: |
| // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmclr.nxv1i1.i64(i64 [[VL:%.*]]) |
| // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] |
| // |
| vbool64_t test_vmclr_m_b64(size_t vl) { return vmclr_m_b64(vl); } |