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llvm / llvm-project / cbd445e4a331114752093746e9d596dafb8580b8 / . / llvm / test / CodeGen / RISCV / rvv / rv32-spill-vector.ll
blob: 96699bb541209479a10b9e70abfca048c2fc5fa3 [file] [log] [blame]
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O0 < %s \
3; RUN: | FileCheck --check-prefix=SPILL-O0 %s
4; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -O2 < %s \
5; RUN: | FileCheck --check-prefix=SPILL-O2 %s
6
7define <vscale x 1 x i32> @spill_lmul_mf2(<vscale x 1 x i32> %va) nounwind {
8; SPILL-O0-LABEL: spill_lmul_mf2:
9; SPILL-O0: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]10; SPILL-O0-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]11; SPILL-O0-NEXT: csrr a0, vlenb
12; SPILL-O0-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]13; SPILL-O0-NEXT: addi a0, sp, 16
14; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]15; SPILL-O0-NEXT: #APP
16; SPILL-O0-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]17; SPILL-O0-NEXT: addi a0, sp, 16
18; SPILL-O0-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]19; SPILL-O0-NEXT: csrr a0, vlenb
20; SPILL-O0-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]21; SPILL-O0-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]22; SPILL-O0-NEXT: ret
23;
24; SPILL-O2-LABEL: spill_lmul_mf2:
25; SPILL-O2: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]26; SPILL-O2-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]27; SPILL-O2-NEXT: csrr a0, vlenb
28; SPILL-O2-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]29; SPILL-O2-NEXT: addi a0, sp, 16
30; SPILL-O2-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]31; SPILL-O2-NEXT: #APP
32; SPILL-O2-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]33; SPILL-O2-NEXT: addi a0, sp, 16
34; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]35; SPILL-O2-NEXT: csrr a0, vlenb
36; SPILL-O2-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]37; SPILL-O2-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]38; SPILL-O2-NEXT: ret
39entry:
40 call void asm sideeffect "",
41 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
42
43 ret <vscale x 1 x i32> %va
44}
45
46define <vscale x 2 x i32> @spill_lmul_1(<vscale x 2 x i32> %va) nounwind {
47; SPILL-O0-LABEL: spill_lmul_1:
48; SPILL-O0: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]49; SPILL-O0-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]50; SPILL-O0-NEXT: csrr a0, vlenb
51; SPILL-O0-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]52; SPILL-O0-NEXT: addi a0, sp, 16
53; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]54; SPILL-O0-NEXT: #APP
55; SPILL-O0-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]56; SPILL-O0-NEXT: addi a0, sp, 16
57; SPILL-O0-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]58; SPILL-O0-NEXT: csrr a0, vlenb
59; SPILL-O0-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]60; SPILL-O0-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]61; SPILL-O0-NEXT: ret
62;
63; SPILL-O2-LABEL: spill_lmul_1:
64; SPILL-O2: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]65; SPILL-O2-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]66; SPILL-O2-NEXT: csrr a0, vlenb
67; SPILL-O2-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]68; SPILL-O2-NEXT: addi a0, sp, 16
69; SPILL-O2-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]70; SPILL-O2-NEXT: #APP
71; SPILL-O2-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]72; SPILL-O2-NEXT: addi a0, sp, 16
73; SPILL-O2-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]74; SPILL-O2-NEXT: csrr a0, vlenb
75; SPILL-O2-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]76; SPILL-O2-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]77; SPILL-O2-NEXT: ret
78entry:
79 call void asm sideeffect "",
80 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
81
82 ret <vscale x 2 x i32> %va
83}
84
85define <vscale x 4 x i32> @spill_lmul_2(<vscale x 4 x i32> %va) nounwind {
86; SPILL-O0-LABEL: spill_lmul_2:
87; SPILL-O0: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]88; SPILL-O0-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]89; SPILL-O0-NEXT: csrr a0, vlenb
90; SPILL-O0-NEXT: slli a0, a0, 1
91; SPILL-O0-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]92; SPILL-O0-NEXT: addi a0, sp, 16
93; SPILL-O0-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]94; SPILL-O0-NEXT: #APP
95; SPILL-O0-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]96; SPILL-O0-NEXT: addi a0, sp, 16
97; SPILL-O0-NEXT: vl2re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]98; SPILL-O0-NEXT: csrr a0, vlenb
99; SPILL-O0-NEXT: slli a0, a0, 1
100; SPILL-O0-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]101; SPILL-O0-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]102; SPILL-O0-NEXT: ret
103;
104; SPILL-O2-LABEL: spill_lmul_2:
105; SPILL-O2: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]106; SPILL-O2-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]107; SPILL-O2-NEXT: csrr a0, vlenb
108; SPILL-O2-NEXT: slli a0, a0, 1
109; SPILL-O2-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]110; SPILL-O2-NEXT: addi a0, sp, 16
111; SPILL-O2-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]112; SPILL-O2-NEXT: #APP
113; SPILL-O2-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]114; SPILL-O2-NEXT: addi a0, sp, 16
115; SPILL-O2-NEXT: vl2re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]116; SPILL-O2-NEXT: csrr a0, vlenb
117; SPILL-O2-NEXT: slli a0, a0, 1
118; SPILL-O2-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]119; SPILL-O2-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]120; SPILL-O2-NEXT: ret
121entry:
122 call void asm sideeffect "",
123 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
124
125 ret <vscale x 4 x i32> %va
126}
127
128define <vscale x 8 x i32> @spill_lmul_4(<vscale x 8 x i32> %va) nounwind {
129; SPILL-O0-LABEL: spill_lmul_4:
130; SPILL-O0: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]131; SPILL-O0-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]132; SPILL-O0-NEXT: csrr a0, vlenb
133; SPILL-O0-NEXT: slli a0, a0, 2
134; SPILL-O0-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]135; SPILL-O0-NEXT: addi a0, sp, 16
136; SPILL-O0-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]137; SPILL-O0-NEXT: #APP
138; SPILL-O0-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]139; SPILL-O0-NEXT: addi a0, sp, 16
140; SPILL-O0-NEXT: vl4re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]141; SPILL-O0-NEXT: csrr a0, vlenb
142; SPILL-O0-NEXT: slli a0, a0, 2
143; SPILL-O0-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]144; SPILL-O0-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]145; SPILL-O0-NEXT: ret
146;
147; SPILL-O2-LABEL: spill_lmul_4:
148; SPILL-O2: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]149; SPILL-O2-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]150; SPILL-O2-NEXT: csrr a0, vlenb
151; SPILL-O2-NEXT: slli a0, a0, 2
152; SPILL-O2-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]153; SPILL-O2-NEXT: addi a0, sp, 16
154; SPILL-O2-NEXT: vs4r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]155; SPILL-O2-NEXT: #APP
156; SPILL-O2-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]157; SPILL-O2-NEXT: addi a0, sp, 16
158; SPILL-O2-NEXT: vl4re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]159; SPILL-O2-NEXT: csrr a0, vlenb
160; SPILL-O2-NEXT: slli a0, a0, 2
161; SPILL-O2-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]162; SPILL-O2-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]163; SPILL-O2-NEXT: ret
164entry:
165 call void asm sideeffect "",
166 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
167
168 ret <vscale x 8 x i32> %va
169}
170
171define <vscale x 16 x i32> @spill_lmul_8(<vscale x 16 x i32> %va) nounwind {
172; SPILL-O0-LABEL: spill_lmul_8:
173; SPILL-O0: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]174; SPILL-O0-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]175; SPILL-O0-NEXT: csrr a0, vlenb
176; SPILL-O0-NEXT: slli a0, a0, 3
177; SPILL-O0-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]178; SPILL-O0-NEXT: addi a0, sp, 16
179; SPILL-O0-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]180; SPILL-O0-NEXT: #APP
181; SPILL-O0-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]182; SPILL-O0-NEXT: addi a0, sp, 16
183; SPILL-O0-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]184; SPILL-O0-NEXT: csrr a0, vlenb
185; SPILL-O0-NEXT: slli a0, a0, 3
186; SPILL-O0-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]187; SPILL-O0-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]188; SPILL-O0-NEXT: ret
189;
190; SPILL-O2-LABEL: spill_lmul_8:
191; SPILL-O2: # %bb.0: # %entry
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]192; SPILL-O2-NEXT: addi sp, sp, -16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]193; SPILL-O2-NEXT: csrr a0, vlenb
194; SPILL-O2-NEXT: slli a0, a0, 3
195; SPILL-O2-NEXT: sub sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]196; SPILL-O2-NEXT: addi a0, sp, 16
197; SPILL-O2-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]198; SPILL-O2-NEXT: #APP
199; SPILL-O2-NEXT: #NO_APP
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]200; SPILL-O2-NEXT: addi a0, sp, 16
201; SPILL-O2-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]202; SPILL-O2-NEXT: csrr a0, vlenb
203; SPILL-O2-NEXT: slli a0, a0, 3
204; SPILL-O2-NEXT: add sp, sp, a0
luxufana9b9c642021-02-20 14:02:56 +0800[diff] [blame]205; SPILL-O2-NEXT: addi sp, sp, 16
Hsiangkai Wanga3c783d2021-01-08 14:42:59 +0800[diff] [blame]206; SPILL-O2-NEXT: ret
207entry:
208 call void asm sideeffect "",
209 "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
210
211 ret <vscale x 16 x i32> %va
212}