blob: be31078d86860e0196e5c67a67945f0b29e4f6de [file] [log] [blame]
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -05001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Fangrui Song9e9907f2024-01-16 21:54:58 -08002; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
Tom Stellard58ac7442014-04-29 23:12:48 +00003;
Tom Stellard58ac7442014-04-29 23:12:48 +00004; Most SALU instructions ignore control flow, so we need to make sure
5; they don't overwrite values from other blocks.
6
Tom Stellard744b99b2014-09-24 01:33:28 +00007; If the branch decision is made based on a value in an SGPR then all
8; threads will execute the same code paths, so we don't need to worry
9; about instructions in different blocks overwriting each other.
Tom Stellard58ac7442014-04-29 23:12:48 +000010
Nikita Popovbdf2fbb2022-12-19 12:39:01 +010011define amdgpu_kernel void @sgpr_if_else_salu_br(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -050012; SI-LABEL: sgpr_if_else_salu_br:
13; SI: ; %bb.0: ; %entry
Shilei Tian6548b632024-11-08 20:21:16 -050014; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
15; SI-NEXT: s_load_dword s6, s[4:5], 0xf
QingShan Zhang1ffb4682020-08-07 10:20:58 +000016; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050017; SI-NEXT: s_cmp_lg_u32 s0, 0
Jay Foadd2e5d352022-01-31 16:56:32 +000018; SI-NEXT: s_cbranch_scc0 .LBB0_4
QingShan Zhang1ffb4682020-08-07 10:20:58 +000019; SI-NEXT: ; %bb.1: ; %else
Shilei Tian6548b632024-11-08 20:21:16 -050020; SI-NEXT: s_add_i32 s3, s3, s6
Jay Foadd2e5d352022-01-31 16:56:32 +000021; SI-NEXT: s_cbranch_execnz .LBB0_3
22; SI-NEXT: .LBB0_2: ; %if
Shilei Tian6548b632024-11-08 20:21:16 -050023; SI-NEXT: s_sub_i32 s3, s1, s2
Jay Foadd2e5d352022-01-31 16:56:32 +000024; SI-NEXT: .LBB0_3: ; %endif
Shilei Tian6548b632024-11-08 20:21:16 -050025; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
26; SI-NEXT: s_add_i32 s0, s3, s0
27; SI-NEXT: s_mov_b32 s7, 0xf000
28; SI-NEXT: s_mov_b32 s6, -1
29; SI-NEXT: v_mov_b32_e32 v0, s0
Carl Ritsonc3163322022-10-06 09:06:32 +090030; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050031; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
QingShan Zhang1ffb4682020-08-07 10:20:58 +000032; SI-NEXT: s_endpgm
Jay Foadd2e5d352022-01-31 16:56:32 +000033; SI-NEXT: .LBB0_4:
Shilei Tian6548b632024-11-08 20:21:16 -050034; SI-NEXT: ; implicit-def: $sgpr3
Jay Foadd2e5d352022-01-31 16:56:32 +000035; SI-NEXT: s_branch .LBB0_2
hsmahesha49055362020-07-17 11:40:10 +053036
Tom Stellard58ac7442014-04-29 23:12:48 +000037entry:
38 %0 = icmp eq i32 %a, 0
39 br i1 %0, label %if, label %else
40
41if:
Matt Arsenaultad55ee52016-12-06 01:02:51 +000042 %1 = sub i32 %b, %c
43 br label %endif
44
45else:
46 %2 = add i32 %d, %e
47 br label %endif
48
49endif:
50 %3 = phi i32 [%1, %if], [%2, %else]
51 %4 = add i32 %3, %a
Nikita Popovbdf2fbb2022-12-19 12:39:01 +010052 store i32 %4, ptr addrspace(1) %out
Matt Arsenaultad55ee52016-12-06 01:02:51 +000053 ret void
54}
55
Nikita Popovbdf2fbb2022-12-19 12:39:01 +010056define amdgpu_kernel void @sgpr_if_else_salu_br_opt(ptr addrspace(1) %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -050057; SI-LABEL: sgpr_if_else_salu_br_opt:
58; SI: ; %bb.0: ; %entry
Shilei Tian6548b632024-11-08 20:21:16 -050059; SI-NEXT: s_load_dword s2, s[4:5], 0x13
QingShan Zhang1ffb4682020-08-07 10:20:58 +000060; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050061; SI-NEXT: s_cmp_lg_u32 s2, 0
Jay Foadd2e5d352022-01-31 16:56:32 +000062; SI-NEXT: s_cbranch_scc0 .LBB1_4
QingShan Zhang1ffb4682020-08-07 10:20:58 +000063; SI-NEXT: ; %bb.1: ; %else
Shilei Tian6548b632024-11-08 20:21:16 -050064; SI-NEXT: s_load_dword s0, s[4:5], 0x2e
65; SI-NEXT: s_load_dword s1, s[4:5], 0x37
QingShan Zhang1ffb4682020-08-07 10:20:58 +000066; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050067; SI-NEXT: s_add_i32 s3, s0, s1
Jay Foadd2e5d352022-01-31 16:56:32 +000068; SI-NEXT: s_cbranch_execnz .LBB1_3
69; SI-NEXT: .LBB1_2: ; %if
Shilei Tian6548b632024-11-08 20:21:16 -050070; SI-NEXT: s_load_dword s0, s[4:5], 0x1c
71; SI-NEXT: s_load_dword s1, s[4:5], 0x25
QingShan Zhang1ffb4682020-08-07 10:20:58 +000072; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050073; SI-NEXT: s_add_i32 s3, s0, s1
Jay Foadd2e5d352022-01-31 16:56:32 +000074; SI-NEXT: .LBB1_3: ; %endif
Shilei Tian6548b632024-11-08 20:21:16 -050075; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
76; SI-NEXT: s_add_i32 s0, s3, s2
77; SI-NEXT: s_mov_b32 s7, 0xf000
78; SI-NEXT: s_mov_b32 s6, -1
79; SI-NEXT: v_mov_b32_e32 v0, s0
Carl Ritsonc3163322022-10-06 09:06:32 +090080; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -050081; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
QingShan Zhang1ffb4682020-08-07 10:20:58 +000082; SI-NEXT: s_endpgm
Jay Foadd2e5d352022-01-31 16:56:32 +000083; SI-NEXT: .LBB1_4:
Shilei Tian6548b632024-11-08 20:21:16 -050084; SI-NEXT: ; implicit-def: $sgpr3
Jay Foadd2e5d352022-01-31 16:56:32 +000085; SI-NEXT: s_branch .LBB1_2
hsmahesha49055362020-07-17 11:40:10 +053086
Matt Arsenaultad55ee52016-12-06 01:02:51 +000087entry:
Matt Arsenault8c4a3522018-06-26 19:10:00 +000088 %cmp0 = icmp eq i32 %a, 0
89 br i1 %cmp0, label %if, label %else
Matt Arsenaultad55ee52016-12-06 01:02:51 +000090
91if:
Matt Arsenault8c4a3522018-06-26 19:10:00 +000092 %add0 = add i32 %b, %c
Tom Stellard58ac7442014-04-29 23:12:48 +000093 br label %endif
94
95else:
Matt Arsenault8c4a3522018-06-26 19:10:00 +000096 %add1 = add i32 %d, %e
Tom Stellard58ac7442014-04-29 23:12:48 +000097 br label %endif
98
99endif:
Matt Arsenault8c4a3522018-06-26 19:10:00 +0000100 %phi = phi i32 [%add0, %if], [%add1, %else]
101 %add2 = add i32 %phi, %a
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100102 store i32 %add2, ptr addrspace(1) %out
Tom Stellard58ac7442014-04-29 23:12:48 +0000103 ret void
104}
Tom Stellard744b99b2014-09-24 01:33:28 +0000105
106; The two S_ADD instructions should write to different registers, since
107; different threads will take different control flow paths.
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100108define amdgpu_kernel void @sgpr_if_else_valu_br(ptr addrspace(1) %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) {
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500109; SI-LABEL: sgpr_if_else_valu_br:
110; SI: ; %bb.0: ; %entry
Shilei Tian6548b632024-11-08 20:21:16 -0500111; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xc
Austin Kerbowda067ed2021-11-10 09:59:31 -0800112; SI-NEXT: v_cvt_f32_u32_e32 v0, v0
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400113; SI-NEXT: ; implicit-def: $sgpr8
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500114; SI-NEXT: v_cmp_lg_f32_e32 vcc, 0, v0
Shilei Tian6548b632024-11-08 20:21:16 -0500115; SI-NEXT: s_and_saveexec_b64 s[6:7], vcc
116; SI-NEXT: s_xor_b64 s[6:7], exec, s[6:7]
RamNalamothu18f935122021-11-20 01:53:38 +0530117; SI-NEXT: s_cbranch_execz .LBB2_2
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500118; SI-NEXT: ; %bb.1: ; %else
119; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -0500120; SI-NEXT: s_add_i32 s8, s2, s3
RamNalamothu18f935122021-11-20 01:53:38 +0530121; SI-NEXT: .LBB2_2: ; %Flow
Shilei Tianca336492024-11-08 16:36:10 -0500122; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -0500123; SI-NEXT: s_or_saveexec_b64 s[2:3], s[6:7]
124; SI-NEXT: v_mov_b32_e32 v0, s8
125; SI-NEXT: s_xor_b64 exec, exec, s[2:3]
126; SI-NEXT: ; %bb.3: ; %if
127; SI-NEXT: s_add_i32 s0, s0, s1
128; SI-NEXT: v_mov_b32_e32 v0, s0
129; SI-NEXT: ; %bb.4: ; %endif
130; SI-NEXT: s_or_b64 exec, exec, s[2:3]
131; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
Carl Ritsonc3163322022-10-06 09:06:32 +0900132; SI-NEXT: s_mov_b32 s3, 0xf000
133; SI-NEXT: s_mov_b32 s2, -1
134; SI-NEXT: s_waitcnt lgkmcnt(0)
135; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500136; SI-NEXT: s_endpgm
Tom Stellard744b99b2014-09-24 01:33:28 +0000137entry:
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000138 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
Tom Stellard744b99b2014-09-24 01:33:28 +0000139 %tid_f = uitofp i32 %tid to float
140 %tmp1 = fcmp ueq float %tid_f, 0.0
141 br i1 %tmp1, label %if, label %else
142
143if:
144 %tmp2 = add i32 %b, %c
145 br label %endif
146
147else:
148 %tmp3 = add i32 %d, %e
149 br label %endif
150
151endif:
152 %tmp4 = phi i32 [%tmp2, %if], [%tmp3, %else]
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100153 store i32 %tmp4, ptr addrspace(1) %out
Tom Stellard744b99b2014-09-24 01:33:28 +0000154 ret void
155}
156
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100157define amdgpu_kernel void @sgpr_if_else_valu_cmp_phi_br(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500158; SI-LABEL: sgpr_if_else_valu_cmp_phi_br:
159; SI: ; %bb.0: ; %entry
Shilei Tian6548b632024-11-08 20:21:16 -0500160; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
161; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
162; SI-NEXT: s_mov_b32 s6, 0
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500163; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
Guozhi Wei11e86862022-11-14 19:34:59 +0000164; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400165; SI-NEXT: ; implicit-def: $sgpr8_sgpr9
166; SI-NEXT: s_and_saveexec_b64 s[10:11], vcc
167; SI-NEXT: s_xor_b64 s[10:11], exec, s[10:11]
RamNalamothu18f935122021-11-20 01:53:38 +0530168; SI-NEXT: s_cbranch_execz .LBB3_2
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500169; SI-NEXT: ; %bb.1: ; %else
Shilei Tian6548b632024-11-08 20:21:16 -0500170; SI-NEXT: s_mov_b32 s7, 0xf000
Ruiling Song208332d2021-04-19 10:45:41 +0800171; SI-NEXT: v_mov_b32_e32 v1, 0
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500172; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -0500173; SI-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500174; SI-NEXT: s_waitcnt vmcnt(0)
Ruiling Song208332d2021-04-19 10:45:41 +0800175; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v0
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400176; SI-NEXT: s_and_b64 s[8:9], vcc, exec
Ruiling Song208332d2021-04-19 10:45:41 +0800177; SI-NEXT: ; implicit-def: $vgpr0
RamNalamothu18f935122021-11-20 01:53:38 +0530178; SI-NEXT: .LBB3_2: ; %Flow
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400179; SI-NEXT: s_waitcnt lgkmcnt(0)
Shilei Tian6548b632024-11-08 20:21:16 -0500180; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[10:11]
RamNalamothu18f935122021-11-20 01:53:38 +0530181; SI-NEXT: s_cbranch_execz .LBB3_4
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500182; SI-NEXT: ; %bb.3: ; %if
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400183; SI-NEXT: s_mov_b32 s15, 0xf000
184; SI-NEXT: s_mov_b32 s14, 0
Shilei Tian6548b632024-11-08 20:21:16 -0500185; SI-NEXT: s_mov_b64 s[12:13], s[2:3]
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500186; SI-NEXT: v_mov_b32_e32 v1, 0
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400187; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
188; SI-NEXT: s_andn2_b64 s[2:3], s[8:9], exec
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500189; SI-NEXT: s_waitcnt vmcnt(0)
190; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
191; SI-NEXT: s_and_b64 s[6:7], vcc, exec
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400192; SI-NEXT: s_or_b64 s[8:9], s[2:3], s[6:7]
RamNalamothu18f935122021-11-20 01:53:38 +0530193; SI-NEXT: .LBB3_4: ; %endif
Shilei Tian6548b632024-11-08 20:21:16 -0500194; SI-NEXT: s_or_b64 exec, exec, s[4:5]
195; SI-NEXT: s_mov_b32 s3, 0xf000
196; SI-NEXT: s_mov_b32 s2, -1
Matt Arsenaultd719f1c2021-08-03 19:09:44 -0400197; SI-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[8:9]
Shilei Tian6548b632024-11-08 20:21:16 -0500198; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
Matt Arsenaultc28f1fa2020-01-31 18:14:50 -0500199; SI-NEXT: s_endpgm
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000200entry:
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000201 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000202 %tmp1 = icmp eq i32 %tid, 0
203 br i1 %tmp1, label %if, label %else
204
205if:
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100206 %gep.if = getelementptr i32, ptr addrspace(1) %a, i32 %tid
207 %a.val = load i32, ptr addrspace(1) %gep.if
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000208 %cmp.if = icmp eq i32 %a.val, 0
209 br label %endif
210
211else:
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100212 %gep.else = getelementptr i32, ptr addrspace(1) %b, i32 %tid
213 %b.val = load i32, ptr addrspace(1) %gep.else
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000214 %cmp.else = icmp slt i32 %b.val, 0
215 br label %endif
216
217endif:
218 %tmp4 = phi i1 [%cmp.if, %if], [%cmp.else, %else]
219 %ext = sext i1 %tmp4 to i32
Nikita Popovbdf2fbb2022-12-19 12:39:01 +0100220 store i32 %ext, ptr addrspace(1) %out
Matt Arsenaultbecd6562014-12-03 05:22:35 +0000221 ret void
222}
223
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000224declare i32 @llvm.amdgcn.workitem.id.x() #0
Tom Stellard744b99b2014-09-24 01:33:28 +0000225
226attributes #0 = { readnone }