[NFC][Test] Format the test with script update_llc_test_checks.py
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
index f423672b..07c2575 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-control-flow.ll
@@ -11,27 +11,27 @@
define amdgpu_kernel void @sgpr_if_else_salu_br(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br:
; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
-; SI-NEXT: s_load_dword s0, s[0:1], 0xf
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_cmp_lg_u32 s8, 0
-; SI-NEXT: s_cbranch_scc0 BB0_2
-; SI-NEXT:; %bb.1: ; %else
-; SI-NEXT: s_add_i32 s0, s11, s0
-; SI-NEXT: s_cbranch_execz BB0_3
-; SI-NEXT: s_branch BB0_4
-; SI-NEXT:BB0_2:
-; SI-NEXT: ; implicit-def: $sgpr0
-; SI-NEXT:BB0_3: ; %if
-; SI-NEXT: s_sub_i32 s0, s9, s10
-; SI-NEXT:BB0_4: ; %endif
-; SI-NEXT: s_add_i32 s0, s0, s8
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0xb
+; SI-NEXT: s_load_dword s0, s[0:1], 0xf
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s8, 0
+; SI-NEXT: s_cbranch_scc0 BB0_2
+; SI-NEXT: ; %bb.1: ; %else
+; SI-NEXT: s_add_i32 s0, s11, s0
+; SI-NEXT: s_cbranch_execz BB0_3
+; SI-NEXT: s_branch BB0_4
+; SI-NEXT: BB0_2:
+; SI-NEXT: ; implicit-def: $sgpr0
+; SI-NEXT: BB0_3: ; %if
+; SI-NEXT: s_sub_i32 s0, s9, s10
+; SI-NEXT: BB0_4: ; %endif
+; SI-NEXT: s_add_i32 s0, s0, s8
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
entry:
%0 = icmp eq i32 %a, 0
@@ -55,32 +55,32 @@
define amdgpu_kernel void @sgpr_if_else_salu_br_opt(i32 addrspace(1)* %out, [8 x i32], i32 %a, [8 x i32], i32 %b, [8 x i32], i32 %c, [8 x i32], i32 %d, [8 x i32], i32 %e) {
; SI-LABEL: sgpr_if_else_salu_br_opt:
; SI: ; %bb.0: ; %entry
-; SI-NEXT: s_load_dword s2, s[0:1], 0x13
-; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_cmp_lg_u32 s2, 0
-; SI-NEXT: s_cbranch_scc0 BB1_2
-; SI-NEXT:; %bb.1: ; %else
-; SI-NEXT: s_load_dword s3, s[0:1], 0x2e
-; SI-NEXT: s_load_dword s6, s[0:1], 0x37
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_add_i32 s3, s3, s6
-; SI-NEXT: s_cbranch_execz BB1_3
-; SI-NEXT: s_branch BB1_4
-; SI-NEXT:BB1_2:
-; SI-NEXT: ; implicit-def: $sgpr3
-; SI-NEXT:BB1_3: ; %if
-; SI-NEXT: s_load_dword s3, s[0:1], 0x1c
-; SI-NEXT: s_load_dword s0, s[0:1], 0x25
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_add_i32 s3, s3, s0
-; SI-NEXT:BB1_4: ; %endif
-; SI-NEXT: s_add_i32 s0, s3, s2
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; SI-NEXT: s_endpgm
+; SI-NEXT: s_load_dword s2, s[0:1], 0x13
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s2, 0
+; SI-NEXT: s_cbranch_scc0 BB1_2
+; SI-NEXT: ; %bb.1: ; %else
+; SI-NEXT: s_load_dword s3, s[0:1], 0x2e
+; SI-NEXT: s_load_dword s6, s[0:1], 0x37
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_add_i32 s3, s3, s6
+; SI-NEXT: s_cbranch_execz BB1_3
+; SI-NEXT: s_branch BB1_4
+; SI-NEXT: BB1_2:
+; SI-NEXT: ; implicit-def: $sgpr3
+; SI-NEXT: BB1_3: ; %if
+; SI-NEXT: s_load_dword s3, s[0:1], 0x1c
+; SI-NEXT: s_load_dword s0, s[0:1], 0x25
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_add_i32 s3, s3, s0
+; SI-NEXT: BB1_4: ; %endif
+; SI-NEXT: s_add_i32 s0, s3, s2
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
entry:
%cmp0 = icmp eq i32 %a, 0
