blob: e10dbdaeb4f26657835d91d7005aad94904f804e [file] [log] [blame]
Simon Pilgrim29412ee2015-11-28 14:15:40 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Craig Topper7eb0e7c2016-09-29 05:54:43 +00002; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX2
3; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2
4; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=X32 --check-prefix=X32-AVX512VL
5; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx512vl,+avx512dq | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VL
Nadav Rotem1ec141d2011-11-18 02:49:55 +00006
Nadav Rotem1ec141d2011-11-18 02:49:55 +00007define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00008; X32-LABEL: BB16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00009; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000010; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
11; X32-NEXT: vpbroadcastb (%eax), %xmm0
12; X32-NEXT: retl
13;
14; X64-LABEL: BB16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000015; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000016; X64-NEXT: vpbroadcastb (%rdi), %xmm0
17; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +000018entry:
David Blaikiea79ac142015-02-27 21:17:42 +000019 %q = load i8, i8* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +000020 %q0 = insertelement <16 x i8> undef, i8 %q, i32 0
21 %q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
22 %q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
23 %q3 = insertelement <16 x i8> %q2, i8 %q, i32 3
24 %q4 = insertelement <16 x i8> %q3, i8 %q, i32 4
25 %q5 = insertelement <16 x i8> %q4, i8 %q, i32 5
26 %q6 = insertelement <16 x i8> %q5, i8 %q, i32 6
27 %q7 = insertelement <16 x i8> %q6, i8 %q, i32 7
28 %q8 = insertelement <16 x i8> %q7, i8 %q, i32 8
29 %q9 = insertelement <16 x i8> %q8, i8 %q, i32 9
30 %qa = insertelement <16 x i8> %q9, i8 %q, i32 10
31 %qb = insertelement <16 x i8> %qa, i8 %q, i32 11
32 %qc = insertelement <16 x i8> %qb, i8 %q, i32 12
33 %qd = insertelement <16 x i8> %qc, i8 %q, i32 13
34 %qe = insertelement <16 x i8> %qd, i8 %q, i32 14
35 %qf = insertelement <16 x i8> %qe, i8 %q, i32 15
36 ret <16 x i8> %qf
37}
Simon Pilgrim29412ee2015-11-28 14:15:40 +000038
Nadav Rotem1ec141d2011-11-18 02:49:55 +000039define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000040; X32-LABEL: BB32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000041; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000042; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
43; X32-NEXT: vpbroadcastb (%eax), %ymm0
44; X32-NEXT: retl
45;
46; X64-LABEL: BB32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000047; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000048; X64-NEXT: vpbroadcastb (%rdi), %ymm0
49; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +000050entry:
David Blaikiea79ac142015-02-27 21:17:42 +000051 %q = load i8, i8* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +000052 %q0 = insertelement <32 x i8> undef, i8 %q, i32 0
53 %q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
54 %q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
55 %q3 = insertelement <32 x i8> %q2, i8 %q, i32 3
56 %q4 = insertelement <32 x i8> %q3, i8 %q, i32 4
57 %q5 = insertelement <32 x i8> %q4, i8 %q, i32 5
58 %q6 = insertelement <32 x i8> %q5, i8 %q, i32 6
59 %q7 = insertelement <32 x i8> %q6, i8 %q, i32 7
60 %q8 = insertelement <32 x i8> %q7, i8 %q, i32 8
61 %q9 = insertelement <32 x i8> %q8, i8 %q, i32 9
62 %qa = insertelement <32 x i8> %q9, i8 %q, i32 10
63 %qb = insertelement <32 x i8> %qa, i8 %q, i32 11
64 %qc = insertelement <32 x i8> %qb, i8 %q, i32 12
65 %qd = insertelement <32 x i8> %qc, i8 %q, i32 13
66 %qe = insertelement <32 x i8> %qd, i8 %q, i32 14
67 %qf = insertelement <32 x i8> %qe, i8 %q, i32 15
68
69 %q20 = insertelement <32 x i8> %qf, i8 %q, i32 16
70 %q21 = insertelement <32 x i8> %q20, i8 %q, i32 17
71 %q22 = insertelement <32 x i8> %q21, i8 %q, i32 18
72 %q23 = insertelement <32 x i8> %q22, i8 %q, i32 19
73 %q24 = insertelement <32 x i8> %q23, i8 %q, i32 20
74 %q25 = insertelement <32 x i8> %q24, i8 %q, i32 21
75 %q26 = insertelement <32 x i8> %q25, i8 %q, i32 22
76 %q27 = insertelement <32 x i8> %q26, i8 %q, i32 23
77 %q28 = insertelement <32 x i8> %q27, i8 %q, i32 24
78 %q29 = insertelement <32 x i8> %q28, i8 %q, i32 25
79 %q2a = insertelement <32 x i8> %q29, i8 %q, i32 26
80 %q2b = insertelement <32 x i8> %q2a, i8 %q, i32 27
81 %q2c = insertelement <32 x i8> %q2b, i8 %q, i32 28
82 %q2d = insertelement <32 x i8> %q2c, i8 %q, i32 29
83 %q2e = insertelement <32 x i8> %q2d, i8 %q, i32 30
84 %q2f = insertelement <32 x i8> %q2e, i8 %q, i32 31
85 ret <32 x i8> %q2f
86}
Nadav Rotem1ec141d2011-11-18 02:49:55 +000087
88define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000089; X32-LABEL: W16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000090; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000091; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
92; X32-NEXT: vpbroadcastw (%eax), %xmm0
93; X32-NEXT: retl
94;
95; X64-LABEL: W16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +000096; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +000097; X64-NEXT: vpbroadcastw (%rdi), %xmm0
98; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +000099entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000100 %q = load i16, i16* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000101 %q0 = insertelement <8 x i16> undef, i16 %q, i32 0
102 %q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
103 %q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
104 %q3 = insertelement <8 x i16> %q2, i16 %q, i32 3
105 %q4 = insertelement <8 x i16> %q3, i16 %q, i32 4
106 %q5 = insertelement <8 x i16> %q4, i16 %q, i32 5
107 %q6 = insertelement <8 x i16> %q5, i16 %q, i32 6
108 %q7 = insertelement <8 x i16> %q6, i16 %q, i32 7
109 ret <8 x i16> %q7
110}
Simon Pilgrim29412ee2015-11-28 14:15:40 +0000111
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000112define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000113; X32-LABEL: WW16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000114; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000115; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
116; X32-NEXT: vpbroadcastw (%eax), %ymm0
117; X32-NEXT: retl
118;
119; X64-LABEL: WW16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000120; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000121; X64-NEXT: vpbroadcastw (%rdi), %ymm0
122; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000123entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000124 %q = load i16, i16* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000125 %q0 = insertelement <16 x i16> undef, i16 %q, i32 0
126 %q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
127 %q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
128 %q3 = insertelement <16 x i16> %q2, i16 %q, i32 3
129 %q4 = insertelement <16 x i16> %q3, i16 %q, i32 4
130 %q5 = insertelement <16 x i16> %q4, i16 %q, i32 5
131 %q6 = insertelement <16 x i16> %q5, i16 %q, i32 6
132 %q7 = insertelement <16 x i16> %q6, i16 %q, i32 7
133 %q8 = insertelement <16 x i16> %q7, i16 %q, i32 8
134 %q9 = insertelement <16 x i16> %q8, i16 %q, i32 9
135 %qa = insertelement <16 x i16> %q9, i16 %q, i32 10
136 %qb = insertelement <16 x i16> %qa, i16 %q, i32 11
137 %qc = insertelement <16 x i16> %qb, i16 %q, i32 12
138 %qd = insertelement <16 x i16> %qc, i16 %q, i32 13
139 %qe = insertelement <16 x i16> %qd, i16 %q, i32 14
140 %qf = insertelement <16 x i16> %qe, i16 %q, i32 15
141 ret <16 x i16> %qf
142}
Simon Pilgrim29412ee2015-11-28 14:15:40 +0000143
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000144define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000145; X32-LABEL: D32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000146; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000147; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
148; X32-NEXT: vbroadcastss (%eax), %xmm0
149; X32-NEXT: retl
150;
151; X64-LABEL: D32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000152; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000153; X64-NEXT: vbroadcastss (%rdi), %xmm0
154; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000155entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000156 %q = load i32, i32* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000157 %q0 = insertelement <4 x i32> undef, i32 %q, i32 0
158 %q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
159 %q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
160 %q3 = insertelement <4 x i32> %q2, i32 %q, i32 3
161 ret <4 x i32> %q3
162}
Simon Pilgrim29412ee2015-11-28 14:15:40 +0000163
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000164define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000165; X32-LABEL: DD32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000166; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000167; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
168; X32-NEXT: vbroadcastss (%eax), %ymm0
169; X32-NEXT: retl
170;
171; X64-LABEL: DD32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000172; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000173; X64-NEXT: vbroadcastss (%rdi), %ymm0
174; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000175entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000176 %q = load i32, i32* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000177 %q0 = insertelement <8 x i32> undef, i32 %q, i32 0
178 %q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
179 %q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
180 %q3 = insertelement <8 x i32> %q2, i32 %q, i32 3
181 %q4 = insertelement <8 x i32> %q3, i32 %q, i32 4
182 %q5 = insertelement <8 x i32> %q4, i32 %q, i32 5
183 %q6 = insertelement <8 x i32> %q5, i32 %q, i32 6
184 %q7 = insertelement <8 x i32> %q6, i32 %q, i32 7
185 ret <8 x i32> %q7
186}
Simon Pilgrim29412ee2015-11-28 14:15:40 +0000187
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000188define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000189; X32-LABEL: Q64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000190; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000191; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Simon Pilgrime95550f2019-02-01 21:41:30 +0000192; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000193; X32-NEXT: retl
194;
195; X64-LABEL: Q64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000196; X64: ## %bb.0: ## %entry
Simon Pilgrime95550f2019-02-01 21:41:30 +0000197; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000198; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000199entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000200 %q = load i64, i64* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000201 %q0 = insertelement <2 x i64> undef, i64 %q, i32 0
202 %q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
203 ret <2 x i64> %q1
204}
Simon Pilgrim29412ee2015-11-28 14:15:40 +0000205
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000206define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
Craig Topperfa875a12017-01-03 05:46:18 +0000207; X32-LABEL: QQ64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000208; X32: ## %bb.0: ## %entry
Craig Topperfa875a12017-01-03 05:46:18 +0000209; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Simon Pilgrim952abce2019-02-19 15:57:09 +0000210; X32-NEXT: vbroadcastsd (%eax), %ymm0
Craig Topperfa875a12017-01-03 05:46:18 +0000211; X32-NEXT: retl
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000212;
213; X64-LABEL: QQ64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000214; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000215; X64-NEXT: vbroadcastsd (%rdi), %ymm0
216; X64-NEXT: retq
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000217entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000218 %q = load i64, i64* %ptr, align 4
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000219 %q0 = insertelement <4 x i64> undef, i64 %q, i32 0
220 %q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
221 %q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
222 %q3 = insertelement <4 x i64> %q2, i64 %q, i32 3
223 ret <4 x i64> %q3
224}
Craig Topper430f3f12012-01-10 08:23:59 +0000225
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000226define <8 x i16> @broadcast_mem_v4i16_v8i16(<4 x i16>* %ptr) {
Craig Toppera5af4a62017-10-15 16:41:17 +0000227; X32-LABEL: broadcast_mem_v4i16_v8i16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000228; X32: ## %bb.0:
Craig Toppera5af4a62017-10-15 16:41:17 +0000229; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
230; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
231; X32-NEXT: retl
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000232;
Craig Toppera5af4a62017-10-15 16:41:17 +0000233; X64-LABEL: broadcast_mem_v4i16_v8i16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000234; X64: ## %bb.0:
Simon Pilgrime95550f2019-02-01 21:41:30 +0000235; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Craig Toppera5af4a62017-10-15 16:41:17 +0000236; X64-NEXT: retq
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000237 %load = load <4 x i16>, <4 x i16>* %ptr
238 %shuf = shufflevector <4 x i16> %load, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
239 ret <8 x i16> %shuf
240}
241
242define <16 x i16> @broadcast_mem_v4i16_v16i16(<4 x i16>* %ptr) {
Craig Toppera5af4a62017-10-15 16:41:17 +0000243; X32-LABEL: broadcast_mem_v4i16_v16i16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000244; X32: ## %bb.0:
Craig Toppera5af4a62017-10-15 16:41:17 +0000245; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Simon Pilgrim63f33832019-01-31 14:04:07 +0000246; X32-NEXT: vbroadcastsd (%eax), %ymm0
Craig Toppera5af4a62017-10-15 16:41:17 +0000247; X32-NEXT: retl
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000248;
Craig Toppera5af4a62017-10-15 16:41:17 +0000249; X64-LABEL: broadcast_mem_v4i16_v16i16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000250; X64: ## %bb.0:
Craig Toppera5af4a62017-10-15 16:41:17 +0000251; X64-NEXT: vbroadcastsd (%rdi), %ymm0
252; X64-NEXT: retq
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000253 %load = load <4 x i16>, <4 x i16>* %ptr
254 %shuf = shufflevector <4 x i16> %load, <4 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
255 ret <16 x i16> %shuf
256}
257
Simon Pilgrim12301b02015-12-07 09:09:54 +0000258; FIXME: Pointer adjusted broadcasts
259
260define <16 x i8> @load_splat_16i8_16i8_1111111111111111(<16 x i8>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000261; X32-LABEL: load_splat_16i8_16i8_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000262; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000263; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
264; X32-NEXT: vpbroadcastb 1(%eax), %xmm0
265; X32-NEXT: retl
266;
267; X64-LABEL: load_splat_16i8_16i8_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000268; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000269; X64-NEXT: vpbroadcastb 1(%rdi), %xmm0
270; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000271entry:
272 %ld = load <16 x i8>, <16 x i8>* %ptr
273 %ret = shufflevector <16 x i8> %ld, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
274 ret <16 x i8> %ret
275}
276
277define <32 x i8> @load_splat_32i8_16i8_11111111111111111111111111111111(<16 x i8>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000278; X32-LABEL: load_splat_32i8_16i8_11111111111111111111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000279; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000280; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
281; X32-NEXT: vpbroadcastb 1(%eax), %ymm0
282; X32-NEXT: retl
283;
284; X64-LABEL: load_splat_32i8_16i8_11111111111111111111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000285; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000286; X64-NEXT: vpbroadcastb 1(%rdi), %ymm0
287; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000288entry:
289 %ld = load <16 x i8>, <16 x i8>* %ptr
290 %ret = shufflevector <16 x i8> %ld, <16 x i8> undef, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
291 ret <32 x i8> %ret
292}
293
294define <32 x i8> @load_splat_32i8_32i8_11111111111111111111111111111111(<32 x i8>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000295; X32-LABEL: load_splat_32i8_32i8_11111111111111111111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000296; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000297; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
298; X32-NEXT: vpbroadcastb 1(%eax), %ymm0
299; X32-NEXT: retl
300;
301; X64-LABEL: load_splat_32i8_32i8_11111111111111111111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000302; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000303; X64-NEXT: vpbroadcastb 1(%rdi), %ymm0
304; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000305entry:
306 %ld = load <32 x i8>, <32 x i8>* %ptr
307 %ret = shufflevector <32 x i8> %ld, <32 x i8> undef, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
308 ret <32 x i8> %ret
309}
310
311define <8 x i16> @load_splat_8i16_8i16_11111111(<8 x i16>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000312; X32-LABEL: load_splat_8i16_8i16_11111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000313; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000314; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
315; X32-NEXT: vpbroadcastw 2(%eax), %xmm0
316; X32-NEXT: retl
317;
318; X64-LABEL: load_splat_8i16_8i16_11111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000319; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000320; X64-NEXT: vpbroadcastw 2(%rdi), %xmm0
321; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000322entry:
323 %ld = load <8 x i16>, <8 x i16>* %ptr
324 %ret = shufflevector <8 x i16> %ld, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
325 ret <8 x i16> %ret
326}
327
328define <16 x i16> @load_splat_16i16_8i16_1111111111111111(<8 x i16>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000329; X32-LABEL: load_splat_16i16_8i16_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000330; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000331; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
332; X32-NEXT: vpbroadcastw 2(%eax), %ymm0
333; X32-NEXT: retl
334;
335; X64-LABEL: load_splat_16i16_8i16_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000336; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000337; X64-NEXT: vpbroadcastw 2(%rdi), %ymm0
338; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000339entry:
340 %ld = load <8 x i16>, <8 x i16>* %ptr
341 %ret = shufflevector <8 x i16> %ld, <8 x i16> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
342 ret <16 x i16> %ret
343}
344
345define <16 x i16> @load_splat_16i16_16i16_1111111111111111(<16 x i16>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000346; X32-LABEL: load_splat_16i16_16i16_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000347; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000348; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
349; X32-NEXT: vpbroadcastw 2(%eax), %ymm0
350; X32-NEXT: retl
351;
352; X64-LABEL: load_splat_16i16_16i16_1111111111111111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000353; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000354; X64-NEXT: vpbroadcastw 2(%rdi), %ymm0
355; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000356entry:
357 %ld = load <16 x i16>, <16 x i16>* %ptr
358 %ret = shufflevector <16 x i16> %ld, <16 x i16> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
359 ret <16 x i16> %ret
360}
361
362define <4 x i32> @load_splat_4i32_4i32_1111(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000363; X32-LABEL: load_splat_4i32_4i32_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000364; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000365; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
366; X32-NEXT: vbroadcastss 4(%eax), %xmm0
367; X32-NEXT: retl
368;
369; X64-LABEL: load_splat_4i32_4i32_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000370; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000371; X64-NEXT: vbroadcastss 4(%rdi), %xmm0
372; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000373entry:
374 %ld = load <4 x i32>, <4 x i32>* %ptr
375 %ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
376 ret <4 x i32> %ret
377}
378
379define <8 x i32> @load_splat_8i32_4i32_33333333(<4 x i32>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000380; X32-LABEL: load_splat_8i32_4i32_33333333:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000381; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000382; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
383; X32-NEXT: vbroadcastss 12(%eax), %ymm0
384; X32-NEXT: retl
385;
386; X64-LABEL: load_splat_8i32_4i32_33333333:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000387; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000388; X64-NEXT: vbroadcastss 12(%rdi), %ymm0
389; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000390entry:
391 %ld = load <4 x i32>, <4 x i32>* %ptr
392 %ret = shufflevector <4 x i32> %ld, <4 x i32> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
393 ret <8 x i32> %ret
394}
395
396define <8 x i32> @load_splat_8i32_8i32_55555555(<8 x i32>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000397; X32-LABEL: load_splat_8i32_8i32_55555555:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000398; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000399; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
400; X32-NEXT: vbroadcastss 20(%eax), %ymm0
401; X32-NEXT: retl
402;
403; X64-LABEL: load_splat_8i32_8i32_55555555:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000404; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000405; X64-NEXT: vbroadcastss 20(%rdi), %ymm0
406; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000407entry:
408 %ld = load <8 x i32>, <8 x i32>* %ptr
409 %ret = shufflevector <8 x i32> %ld, <8 x i32> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
410 ret <8 x i32> %ret
411}
412
413define <4 x float> @load_splat_4f32_4f32_1111(<4 x float>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000414; X32-LABEL: load_splat_4f32_4f32_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000415; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000416; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
417; X32-NEXT: vbroadcastss 4(%eax), %xmm0
418; X32-NEXT: retl
419;
420; X64-LABEL: load_splat_4f32_4f32_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000421; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000422; X64-NEXT: vbroadcastss 4(%rdi), %xmm0
423; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000424entry:
425 %ld = load <4 x float>, <4 x float>* %ptr
426 %ret = shufflevector <4 x float> %ld, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
427 ret <4 x float> %ret
428}
429
430define <8 x float> @load_splat_8f32_4f32_33333333(<4 x float>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000431; X32-LABEL: load_splat_8f32_4f32_33333333:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000432; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000433; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
434; X32-NEXT: vbroadcastss 12(%eax), %ymm0
435; X32-NEXT: retl
436;
437; X64-LABEL: load_splat_8f32_4f32_33333333:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000438; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000439; X64-NEXT: vbroadcastss 12(%rdi), %ymm0
440; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000441entry:
442 %ld = load <4 x float>, <4 x float>* %ptr
443 %ret = shufflevector <4 x float> %ld, <4 x float> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
444 ret <8 x float> %ret
445}
446
447define <8 x float> @load_splat_8f32_8f32_55555555(<8 x float>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000448; X32-LABEL: load_splat_8f32_8f32_55555555:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000449; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000450; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
451; X32-NEXT: vbroadcastss 20(%eax), %ymm0
452; X32-NEXT: retl
453;
454; X64-LABEL: load_splat_8f32_8f32_55555555:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000455; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000456; X64-NEXT: vbroadcastss 20(%rdi), %ymm0
457; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000458entry:
459 %ld = load <8 x float>, <8 x float>* %ptr
460 %ret = shufflevector <8 x float> %ld, <8 x float> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
461 ret <8 x float> %ret
462}
463
464define <2 x i64> @load_splat_2i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000465; X32-LABEL: load_splat_2i64_2i64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000466; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000467; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Simon Pilgrim5f71c902016-06-28 13:24:05 +0000468; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000469; X32-NEXT: retl
470;
471; X64-LABEL: load_splat_2i64_2i64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000472; X64: ## %bb.0: ## %entry
Simon Pilgrime95550f2019-02-01 21:41:30 +0000473; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000474; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000475entry:
476 %ld = load <2 x i64>, <2 x i64>* %ptr
477 %ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
478 ret <2 x i64> %ret
479}
480
481define <4 x i64> @load_splat_4i64_2i64_1111(<2 x i64>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000482; X32-LABEL: load_splat_4i64_2i64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000483; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000484; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
485; X32-NEXT: vbroadcastsd 8(%eax), %ymm0
486; X32-NEXT: retl
487;
488; X64-LABEL: load_splat_4i64_2i64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000489; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000490; X64-NEXT: vbroadcastsd 8(%rdi), %ymm0
491; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000492entry:
493 %ld = load <2 x i64>, <2 x i64>* %ptr
494 %ret = shufflevector <2 x i64> %ld, <2 x i64> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
495 ret <4 x i64> %ret
496}
497
498define <4 x i64> @load_splat_4i64_4i64_2222(<4 x i64>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000499; X32-LABEL: load_splat_4i64_4i64_2222:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000500; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000501; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
502; X32-NEXT: vbroadcastsd 16(%eax), %ymm0
503; X32-NEXT: retl
504;
505; X64-LABEL: load_splat_4i64_4i64_2222:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000506; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000507; X64-NEXT: vbroadcastsd 16(%rdi), %ymm0
508; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000509entry:
510 %ld = load <4 x i64>, <4 x i64>* %ptr
511 %ret = shufflevector <4 x i64> %ld, <4 x i64> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
512 ret <4 x i64> %ret
513}
514
515define <2 x double> @load_splat_2f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000516; X32-LABEL: load_splat_2f64_2f64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000517; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000518; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Simon Pilgrimc02b7262016-03-02 11:43:05 +0000519; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000520; X32-NEXT: retl
521;
522; X64-LABEL: load_splat_2f64_2f64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000523; X64: ## %bb.0: ## %entry
Simon Pilgrimc02b7262016-03-02 11:43:05 +0000524; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000525; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000526entry:
527 %ld = load <2 x double>, <2 x double>* %ptr
528 %ret = shufflevector <2 x double> %ld, <2 x double> undef, <2 x i32> <i32 1, i32 1>
529 ret <2 x double> %ret
530}
531
532define <4 x double> @load_splat_4f64_2f64_1111(<2 x double>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000533; X32-LABEL: load_splat_4f64_2f64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000534; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000535; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
536; X32-NEXT: vbroadcastsd 8(%eax), %ymm0
537; X32-NEXT: retl
538;
539; X64-LABEL: load_splat_4f64_2f64_1111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000540; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000541; X64-NEXT: vbroadcastsd 8(%rdi), %ymm0
542; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000543entry:
544 %ld = load <2 x double>, <2 x double>* %ptr
545 %ret = shufflevector <2 x double> %ld, <2 x double> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
546 ret <4 x double> %ret
547}
548
549define <4 x double> @load_splat_4f64_4f64_2222(<4 x double>* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000550; X32-LABEL: load_splat_4f64_4f64_2222:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000551; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000552; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
553; X32-NEXT: vbroadcastsd 16(%eax), %ymm0
554; X32-NEXT: retl
555;
556; X64-LABEL: load_splat_4f64_4f64_2222:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000557; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000558; X64-NEXT: vbroadcastsd 16(%rdi), %ymm0
559; X64-NEXT: retq
Simon Pilgrim12301b02015-12-07 09:09:54 +0000560entry:
561 %ld = load <4 x double>, <4 x double>* %ptr
562 %ret = shufflevector <4 x double> %ld, <4 x double> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
563 ret <4 x double> %ret
564}
565
Craig Topper430f3f12012-01-10 08:23:59 +0000566; make sure that we still don't support broadcast double into 128-bit vector
567; this used to crash
568define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000569; X32-LABEL: I:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000570; X32: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000571; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
572; X32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
573; X32-NEXT: retl
574;
575; X64-LABEL: I:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000576; X64: ## %bb.0: ## %entry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000577; X64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
578; X64-NEXT: retq
Craig Topper430f3f12012-01-10 08:23:59 +0000579entry:
David Blaikiea79ac142015-02-27 21:17:42 +0000580 %q = load double, double* %ptr, align 4
Craig Topper430f3f12012-01-10 08:23:59 +0000581 %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
582 %vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
583 ret <2 x double> %vecinit2.i
584}
Nadav Rotem82609df2012-04-08 12:54:54 +0000585
Nadav Rotem82609df2012-04-08 12:54:54 +0000586define <8 x i32> @V111(<8 x i32> %in) nounwind uwtable readnone ssp {
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000587; X32-AVX2-LABEL: V111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000588; X32-AVX2: ## %bb.0: ## %entry
Craig Topperad140cf2017-07-04 05:46:11 +0000589; X32-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [2,2,2,2,2,2,2,2]
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000590; X32-AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
591; X32-AVX2-NEXT: retl
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000592;
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000593; X64-AVX2-LABEL: V111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000594; X64-AVX2: ## %bb.0: ## %entry
Craig Topperad140cf2017-07-04 05:46:11 +0000595; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} ymm1 = [2,2,2,2,2,2,2,2]
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000596; X64-AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
597; X64-AVX2-NEXT: retq
598;
599; X32-AVX512VL-LABEL: V111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000600; X32-AVX512VL: ## %bb.0: ## %entry
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000601; X32-AVX512VL-NEXT: vpaddd LCPI29_0{1to8}, %ymm0, %ymm0
602; X32-AVX512VL-NEXT: retl
603;
604; X64-AVX512VL-LABEL: V111:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000605; X64-AVX512VL: ## %bb.0: ## %entry
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000606; X64-AVX512VL-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm0
607; X64-AVX512VL-NEXT: retq
Nadav Rotem82609df2012-04-08 12:54:54 +0000608entry:
Sanjay Patel44e3d4c2017-06-18 14:45:23 +0000609 %g = add <8 x i32> %in, <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
Nadav Rotem82609df2012-04-08 12:54:54 +0000610 ret <8 x i32> %g
611}
612
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000613define <8 x float> @V113(<8 x float> %in) nounwind uwtable readnone ssp {
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000614; X32-AVX2-LABEL: V113:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000615; X32-AVX2: ## %bb.0: ## %entry
Craig Topperaa5eb2f2018-10-29 04:52:04 +0000616; X32-AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3]
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000617; X32-AVX2-NEXT: vaddps %ymm1, %ymm0, %ymm0
618; X32-AVX2-NEXT: retl
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000619;
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000620; X64-AVX2-LABEL: V113:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000621; X64-AVX2: ## %bb.0: ## %entry
Craig Topperaa5eb2f2018-10-29 04:52:04 +0000622; X64-AVX2-NEXT: vbroadcastss {{.*#+}} ymm1 = [-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3]
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000623; X64-AVX2-NEXT: vaddps %ymm1, %ymm0, %ymm0
624; X64-AVX2-NEXT: retq
625;
626; X32-AVX512VL-LABEL: V113:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000627; X32-AVX512VL: ## %bb.0: ## %entry
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000628; X32-AVX512VL-NEXT: vaddps LCPI30_0{1to8}, %ymm0, %ymm0
629; X32-AVX512VL-NEXT: retl
630;
631; X64-AVX512VL-LABEL: V113:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000632; X64-AVX512VL: ## %bb.0: ## %entry
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000633; X64-AVX512VL-NEXT: vaddps {{.*}}(%rip){1to8}, %ymm0, %ymm0
634; X64-AVX512VL-NEXT: retq
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000635entry:
636 %g = fadd <8 x float> %in, <float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000>
637 ret <8 x float> %g
638}
639
Nadav Rotem82609df2012-04-08 12:54:54 +0000640define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000641; X32-LABEL: _e2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000642; X32: ## %bb.0:
Craig Topperaa5eb2f2018-10-29 04:52:04 +0000643; X32-NEXT: vbroadcastss {{.*#+}} xmm0 = [-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000644; X32-NEXT: retl
645;
646; X64-LABEL: _e2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000647; X64: ## %bb.0:
Craig Topperaa5eb2f2018-10-29 04:52:04 +0000648; X64-NEXT: vbroadcastss {{.*#+}} xmm0 = [-7.8125E-3,-7.8125E-3,-7.8125E-3,-7.8125E-3]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000649; X64-NEXT: retq
Nadav Rotem82609df2012-04-08 12:54:54 +0000650 %vecinit.i = insertelement <4 x float> undef, float 0xbf80000000000000, i32 0
651 %vecinit2.i = insertelement <4 x float> %vecinit.i, float 0xbf80000000000000, i32 1
652 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
653 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
654 ret <4 x float> %vecinit6.i
655}
656
Nadav Rotemb801ca32012-04-09 07:45:58 +0000657define <8 x i8> @_e4(i8* %ptr) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000658; X32-LABEL: _e4:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000659; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000660; X32-NEXT: vmovaps {{.*#+}} xmm0 = [52,52,52,52,52,52,52,52]
661; X32-NEXT: retl
662;
663; X64-LABEL: _e4:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000664; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000665; X64-NEXT: vmovaps {{.*#+}} xmm0 = [52,52,52,52,52,52,52,52]
666; X64-NEXT: retq
Nadav Rotemb801ca32012-04-09 07:45:58 +0000667 %vecinit0.i = insertelement <8 x i8> undef, i8 52, i32 0
668 %vecinit1.i = insertelement <8 x i8> %vecinit0.i, i8 52, i32 1
669 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 52, i32 2
670 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 52, i32 3
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000671 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 52, i32 4
672 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 52, i32 5
673 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 52, i32 6
674 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 52, i32 7
Nadav Rotemb801ca32012-04-09 07:45:58 +0000675 ret <8 x i8> %vecinit7.i
676}
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000677
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000678define void @crash() nounwind alwaysinline {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000679; X32-LABEL: crash:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000680; X32: ## %bb.0: ## %WGLoopsEntry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000681; X32-NEXT: xorl %eax, %eax
682; X32-NEXT: testb %al, %al
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000683; X32-NEXT: je LBB33_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000684; X32-NEXT: ## %bb.2: ## %ret
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000685; X32-NEXT: retl
Dan Gohman61d15ae2016-01-26 00:03:25 +0000686; X32-NEXT: .p2align 4, 0x90
Alina Sbirleadfd14ad2018-06-20 22:01:04 +0000687; X32-NEXT: LBB33_1: ## %footer329VF
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000688; X32-NEXT: ## =>This Inner Loop Header: Depth=1
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000689; X32-NEXT: jmp LBB33_1
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000690;
691; X64-LABEL: crash:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000692; X64: ## %bb.0: ## %WGLoopsEntry
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000693; X64-NEXT: xorl %eax, %eax
694; X64-NEXT: testb %al, %al
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000695; X64-NEXT: je LBB33_1
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000696; X64-NEXT: ## %bb.2: ## %ret
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000697; X64-NEXT: retq
Dan Gohman61d15ae2016-01-26 00:03:25 +0000698; X64-NEXT: .p2align 4, 0x90
Alina Sbirleadfd14ad2018-06-20 22:01:04 +0000699; X64-NEXT: LBB33_1: ## %footer329VF
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000700; X64-NEXT: ## =>This Inner Loop Header: Depth=1
Simon Pilgrim7a50c8c2016-08-24 12:42:31 +0000701; X64-NEXT: jmp LBB33_1
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000702WGLoopsEntry:
703 br i1 undef, label %ret, label %footer329VF
704
705footer329VF:
706 %A.0.inVF = fmul float undef, 6.553600e+04
707 %B.0.in407VF = fmul <8 x float> undef, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>
708 %A.0VF = fptosi float %A.0.inVF to i32
709 %B.0408VF = fptosi <8 x float> %B.0.in407VF to <8 x i32>
710 %0 = and <8 x i32> %B.0408VF, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
711 %1 = and i32 %A.0VF, 65535
712 %temp1098VF = insertelement <8 x i32> undef, i32 %1, i32 0
713 %vector1099VF = shufflevector <8 x i32> %temp1098VF, <8 x i32> undef, <8 x i32> zeroinitializer
714 br i1 undef, label %preload1201VF, label %footer349VF
715
716preload1201VF:
717 br label %footer349VF
718
719footer349VF:
720 %2 = mul nsw <8 x i32> undef, %0
721 %3 = mul nsw <8 x i32> undef, %vector1099VF
722 br label %footer329VF
723
724ret:
725 ret void
726}
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000727
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000728define <8 x i32> @_inreg0(i32 %scalar) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000729; X32-LABEL: _inreg0:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000730; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000731; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %ymm0
732; X32-NEXT: retl
733;
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000734; X64-AVX2-LABEL: _inreg0:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000735; X64-AVX2: ## %bb.0:
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000736; X64-AVX2-NEXT: vmovd %edi, %xmm0
Simon Pilgrim8893bd92016-12-07 12:10:49 +0000737; X64-AVX2-NEXT: vpbroadcastd %xmm0, %ymm0
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000738; X64-AVX2-NEXT: retq
739;
740; X64-AVX512VL-LABEL: _inreg0:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000741; X64-AVX512VL: ## %bb.0:
Craig Topper7eb0e7c2016-09-29 05:54:43 +0000742; X64-AVX512VL-NEXT: vpbroadcastd %edi, %ymm0
743; X64-AVX512VL-NEXT: retq
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000744 %in = insertelement <8 x i32> undef, i32 %scalar, i32 0
745 %wide = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer
746 ret <8 x i32> %wide
747}
748
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000749define <8 x float> @_inreg1(float %scalar) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000750; X32-LABEL: _inreg1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000751; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000752; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %ymm0
753; X32-NEXT: retl
754;
755; X64-LABEL: _inreg1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000756; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000757; X64-NEXT: vbroadcastss %xmm0, %ymm0
758; X64-NEXT: retq
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000759 %in = insertelement <8 x float> undef, float %scalar, i32 0
760 %wide = shufflevector <8 x float> %in, <8 x float> undef, <8 x i32> zeroinitializer
761 ret <8 x float> %wide
762}
763
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000764define <4 x float> @_inreg2(float %scalar) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000765; X32-LABEL: _inreg2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000766; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000767; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0
768; X32-NEXT: retl
769;
770; X64-LABEL: _inreg2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000771; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000772; X64-NEXT: vbroadcastss %xmm0, %xmm0
773; X64-NEXT: retq
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000774 %in = insertelement <4 x float> undef, float %scalar, i32 0
775 %wide = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> zeroinitializer
776 ret <4 x float> %wide
777}
778
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000779define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000780; X32-LABEL: _inreg3:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000781; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000782; X32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0
783; X32-NEXT: retl
784;
785; X64-LABEL: _inreg3:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000786; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000787; X64-NEXT: vbroadcastsd %xmm0, %ymm0
788; X64-NEXT: retq
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000789 %in = insertelement <4 x double> undef, double %scalar, i32 0
790 %wide = shufflevector <4 x double> %in, <4 x double> undef, <4 x i32> zeroinitializer
791 ret <4 x double> %wide
792}
793
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000794define <8 x float> @_inreg8xfloat(<8 x float> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000795; X32-LABEL: _inreg8xfloat:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000796; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000797; X32-NEXT: vbroadcastss %xmm0, %ymm0
798; X32-NEXT: retl
799;
800; X64-LABEL: _inreg8xfloat:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000801; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000802; X64-NEXT: vbroadcastss %xmm0, %ymm0
803; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000804 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
805 ret <8 x float> %b
806}
807
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000808define <4 x float> @_inreg4xfloat(<4 x float> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000809; X32-LABEL: _inreg4xfloat:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000810; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000811; X32-NEXT: vbroadcastss %xmm0, %xmm0
812; X32-NEXT: retl
813;
814; X64-LABEL: _inreg4xfloat:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000815; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000816; X64-NEXT: vbroadcastss %xmm0, %xmm0
817; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000818 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
819 ret <4 x float> %b
820}
821
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000822define <16 x i16> @_inreg16xi16(<16 x i16> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000823; X32-LABEL: _inreg16xi16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000824; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000825; X32-NEXT: vpbroadcastw %xmm0, %ymm0
826; X32-NEXT: retl
827;
828; X64-LABEL: _inreg16xi16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000829; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000830; X64-NEXT: vpbroadcastw %xmm0, %ymm0
831; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000832 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
833 ret <16 x i16> %b
834}
835
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000836define <8 x i16> @_inreg8xi16(<8 x i16> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000837; X32-LABEL: _inreg8xi16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000838; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000839; X32-NEXT: vpbroadcastw %xmm0, %xmm0
840; X32-NEXT: retl
841;
842; X64-LABEL: _inreg8xi16:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000843; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000844; X64-NEXT: vpbroadcastw %xmm0, %xmm0
845; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000846 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
847 ret <8 x i16> %b
848}
849
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000850define <4 x i64> @_inreg4xi64(<4 x i64> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000851; X32-LABEL: _inreg4xi64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000852; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000853; X32-NEXT: vbroadcastsd %xmm0, %ymm0
854; X32-NEXT: retl
855;
856; X64-LABEL: _inreg4xi64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000857; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000858; X64-NEXT: vbroadcastsd %xmm0, %ymm0
859; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000860 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
861 ret <4 x i64> %b
862}
863
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000864define <2 x i64> @_inreg2xi64(<2 x i64> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000865; X32-LABEL: _inreg2xi64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000866; X32: ## %bb.0:
Simon Pilgrime95550f2019-02-01 21:41:30 +0000867; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000868; X32-NEXT: retl
869;
870; X64-LABEL: _inreg2xi64:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000871; X64: ## %bb.0:
Simon Pilgrime95550f2019-02-01 21:41:30 +0000872; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000873; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000874 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
875 ret <2 x i64> %b
876}
877
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000878define <4 x double> @_inreg4xdouble(<4 x double> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000879; X32-LABEL: _inreg4xdouble:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000880; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000881; X32-NEXT: vbroadcastsd %xmm0, %ymm0
882; X32-NEXT: retl
883;
884; X64-LABEL: _inreg4xdouble:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000885; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000886; X64-NEXT: vbroadcastsd %xmm0, %ymm0
887; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000888 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
889 ret <4 x double> %b
Simon Pilgrim106abe42015-01-26 21:28:32 +0000890}
891
Simon Pilgrim106abe42015-01-26 21:28:32 +0000892define <2 x double> @_inreg2xdouble(<2 x double> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000893; X32-LABEL: _inreg2xdouble:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000894; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000895; X32-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
896; X32-NEXT: retl
897;
898; X64-LABEL: _inreg2xdouble:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000899; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000900; X64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
901; X64-NEXT: retq
Simon Pilgrim106abe42015-01-26 21:28:32 +0000902 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000903 ret <2 x double> %b
904}
905
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000906define <8 x i32> @_inreg8xi32(<8 x i32> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000907; X32-LABEL: _inreg8xi32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000908; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000909; X32-NEXT: vbroadcastss %xmm0, %ymm0
910; X32-NEXT: retl
911;
912; X64-LABEL: _inreg8xi32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000913; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000914; X64-NEXT: vbroadcastss %xmm0, %ymm0
915; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000916 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
917 ret <8 x i32> %b
918}
919
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000920define <4 x i32> @_inreg4xi32(<4 x i32> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000921; X32-LABEL: _inreg4xi32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000922; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000923; X32-NEXT: vbroadcastss %xmm0, %xmm0
924; X32-NEXT: retl
925;
926; X64-LABEL: _inreg4xi32:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000927; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000928; X64-NEXT: vbroadcastss %xmm0, %xmm0
929; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000930 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
931 ret <4 x i32> %b
932}
933
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000934define <32 x i8> @_inreg32xi8(<32 x i8> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000935; X32-LABEL: _inreg32xi8:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000936; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000937; X32-NEXT: vpbroadcastb %xmm0, %ymm0
938; X32-NEXT: retl
939;
940; X64-LABEL: _inreg32xi8:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000941; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000942; X64-NEXT: vpbroadcastb %xmm0, %ymm0
943; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000944 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
945 ret <32 x i8> %b
946}
947
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000948define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000949; X32-LABEL: _inreg16xi8:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000950; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000951; X32-NEXT: vpbroadcastb %xmm0, %xmm0
952; X32-NEXT: retl
953;
954; X64-LABEL: _inreg16xi8:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000955; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000956; X64-NEXT: vpbroadcastb %xmm0, %xmm0
957; X64-NEXT: retq
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000958 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
959 ret <16 x i8> %b
960}
Robert Lougher7d9084f2014-02-11 15:42:46 +0000961
962; These tests check that a vbroadcast instruction is used when we have a splat
963; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
964; (via the insertelements).
965
Robert Lougher7d9084f2014-02-11 15:42:46 +0000966define <8 x float> @splat_concat1(float %f) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000967; X32-LABEL: splat_concat1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000968; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000969; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %ymm0
970; X32-NEXT: retl
971;
972; X64-LABEL: splat_concat1:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000973; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000974; X64-NEXT: vbroadcastss %xmm0, %ymm0
975; X64-NEXT: retq
Robert Lougher7d9084f2014-02-11 15:42:46 +0000976 %1 = insertelement <4 x float> undef, float %f, i32 0
977 %2 = insertelement <4 x float> %1, float %f, i32 1
978 %3 = insertelement <4 x float> %2, float %f, i32 2
979 %4 = insertelement <4 x float> %3, float %f, i32 3
980 %5 = shufflevector <4 x float> %4, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
981 ret <8 x float> %5
982}
983
Robert Lougher7d9084f2014-02-11 15:42:46 +0000984define <8 x float> @splat_concat2(float %f) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000985; X32-LABEL: splat_concat2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000986; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000987; X32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %ymm0
988; X32-NEXT: retl
989;
990; X64-LABEL: splat_concat2:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000991; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +0000992; X64-NEXT: vbroadcastss %xmm0, %ymm0
993; X64-NEXT: retq
Robert Lougher7d9084f2014-02-11 15:42:46 +0000994 %1 = insertelement <4 x float> undef, float %f, i32 0
995 %2 = insertelement <4 x float> %1, float %f, i32 1
996 %3 = insertelement <4 x float> %2, float %f, i32 2
997 %4 = insertelement <4 x float> %3, float %f, i32 3
998 %5 = insertelement <4 x float> undef, float %f, i32 0
999 %6 = insertelement <4 x float> %5, float %f, i32 1
1000 %7 = insertelement <4 x float> %6, float %f, i32 2
1001 %8 = insertelement <4 x float> %7, float %f, i32 3
1002 %9 = shufflevector <4 x float> %4, <4 x float> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1003 ret <8 x float> %9
1004}
1005
Robert Lougher7d9084f2014-02-11 15:42:46 +00001006define <4 x double> @splat_concat3(double %d) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001007; X32-LABEL: splat_concat3:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001008; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001009; X32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0
1010; X32-NEXT: retl
1011;
1012; X64-LABEL: splat_concat3:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001013; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001014; X64-NEXT: vbroadcastsd %xmm0, %ymm0
1015; X64-NEXT: retq
Robert Lougher7d9084f2014-02-11 15:42:46 +00001016 %1 = insertelement <2 x double> undef, double %d, i32 0
1017 %2 = insertelement <2 x double> %1, double %d, i32 1
1018 %3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
1019 ret <4 x double> %3
1020}
1021
Robert Lougher7d9084f2014-02-11 15:42:46 +00001022define <4 x double> @splat_concat4(double %d) {
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001023; X32-LABEL: splat_concat4:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001024; X32: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001025; X32-NEXT: vbroadcastsd {{[0-9]+}}(%esp), %ymm0
1026; X32-NEXT: retl
1027;
1028; X64-LABEL: splat_concat4:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001029; X64: ## %bb.0:
Simon Pilgrim2e7a1842016-01-09 19:59:27 +00001030; X64-NEXT: vbroadcastsd %xmm0, %ymm0
1031; X64-NEXT: retq
Robert Lougher7d9084f2014-02-11 15:42:46 +00001032 %1 = insertelement <2 x double> undef, double %d, i32 0
1033 %2 = insertelement <2 x double> %1, double %d, i32 1
1034 %3 = insertelement <2 x double> undef, double %d, i32 0
1035 %4 = insertelement <2 x double> %3, double %d, i32 1
1036 %5 = shufflevector <2 x double> %2, <2 x double> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1037 ret <4 x double> %5
1038}
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001039
1040; Test cases for <rdar://problem/16074331>.
1041; Instruction selection for broacast instruction fails if
1042; the load cannot be folded into the broadcast.
1043; This happens if the load has initial one use but other uses are
1044; created later, or if selection DAG cannot prove that folding the
1045; load will not create a cycle in the DAG.
1046; Those test cases exerce the latter.
1047
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001048define void @isel_crash_16b(i8* %cV_R.addr) {
Craig Topper15d116a2017-01-03 05:46:10 +00001049; X32-LABEL: isel_crash_16b:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001050; X32: ## %bb.0: ## %eintry
Craig Topper15d116a2017-01-03 05:46:10 +00001051; X32-NEXT: subl $60, %esp
Craig Topper15d116a2017-01-03 05:46:10 +00001052; X32-NEXT: .cfi_def_cfa_offset 64
1053; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1054; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1055; X32-NEXT: vmovaps %xmm0, (%esp)
1056; X32-NEXT: vpbroadcastb (%eax), %xmm1
1057; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
1058; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp)
1059; X32-NEXT: addl $60, %esp
1060; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001061;
Craig Topper15d116a2017-01-03 05:46:10 +00001062; X64-LABEL: isel_crash_16b:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001063; X64: ## %bb.0: ## %eintry
Craig Topper15d116a2017-01-03 05:46:10 +00001064; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1065; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
Nirav Dave3264c1b2018-03-19 20:19:46 +00001066; X64-NEXT: vpbroadcastb (%rdi), %xmm1
Craig Topper15d116a2017-01-03 05:46:10 +00001067; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
1068; X64-NEXT: vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
1069; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001070eintry:
1071 %__a.addr.i = alloca <2 x i64>, align 16
1072 %__b.addr.i = alloca <2 x i64>, align 16
1073 %vCr = alloca <2 x i64>, align 16
1074 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001075 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
1076 %tmp2 = load i8, i8* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001077 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
1078 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
1079 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
1080 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
1081 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
1082 ret void
1083}
1084
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001085define void @isel_crash_32b(i8* %cV_R.addr) {
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001086; X32-LABEL: isel_crash_32b:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001087; X32: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001088; X32-NEXT: pushl %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001089; X32-NEXT: .cfi_def_cfa_offset 8
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001090; X32-NEXT: .cfi_offset %ebp, -8
1091; X32-NEXT: movl %esp, %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001092; X32-NEXT: .cfi_def_cfa_register %ebp
1093; X32-NEXT: andl $-32, %esp
1094; X32-NEXT: subl $128, %esp
1095; X32-NEXT: movl 8(%ebp), %eax
1096; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1097; X32-NEXT: vmovaps %ymm0, (%esp)
1098; X32-NEXT: vpbroadcastb (%eax), %ymm1
1099; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
1100; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
1101; X32-NEXT: movl %ebp, %esp
1102; X32-NEXT: popl %ebp
1103; X32-NEXT: vzeroupper
1104; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001105;
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001106; X64-LABEL: isel_crash_32b:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001107; X64: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001108; X64-NEXT: pushq %rbp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001109; X64-NEXT: .cfi_def_cfa_offset 16
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001110; X64-NEXT: .cfi_offset %rbp, -16
1111; X64-NEXT: movq %rsp, %rbp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001112; X64-NEXT: .cfi_def_cfa_register %rbp
1113; X64-NEXT: andq $-32, %rsp
1114; X64-NEXT: subq $128, %rsp
1115; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1116; X64-NEXT: vmovaps %ymm0, (%rsp)
Nirav Dave3264c1b2018-03-19 20:19:46 +00001117; X64-NEXT: vpbroadcastb (%rdi), %ymm1
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001118; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
1119; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
1120; X64-NEXT: movq %rbp, %rsp
1121; X64-NEXT: popq %rbp
1122; X64-NEXT: vzeroupper
1123; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001124eintry:
1125 %__a.addr.i = alloca <4 x i64>, align 16
1126 %__b.addr.i = alloca <4 x i64>, align 16
1127 %vCr = alloca <4 x i64>, align 16
1128 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001129 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
1130 %tmp2 = load i8, i8* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001131 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
1132 %splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitializer
1133 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
1134 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
1135 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
1136 ret void
1137}
1138
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001139define void @isel_crash_8w(i16* %cV_R.addr) {
Craig Topper15d116a2017-01-03 05:46:10 +00001140; X32-LABEL: isel_crash_8w:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001141; X32: ## %bb.0: ## %entry
Craig Topper15d116a2017-01-03 05:46:10 +00001142; X32-NEXT: subl $60, %esp
Craig Topper15d116a2017-01-03 05:46:10 +00001143; X32-NEXT: .cfi_def_cfa_offset 64
1144; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1145; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1146; X32-NEXT: vmovaps %xmm0, (%esp)
1147; X32-NEXT: vpbroadcastw (%eax), %xmm1
1148; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
1149; X32-NEXT: vmovdqa %xmm1, {{[0-9]+}}(%esp)
1150; X32-NEXT: addl $60, %esp
1151; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001152;
Craig Topper15d116a2017-01-03 05:46:10 +00001153; X64-LABEL: isel_crash_8w:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001154; X64: ## %bb.0: ## %entry
Craig Topper15d116a2017-01-03 05:46:10 +00001155; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1156; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
Nirav Dave3264c1b2018-03-19 20:19:46 +00001157; X64-NEXT: vpbroadcastw (%rdi), %xmm1
Craig Topper15d116a2017-01-03 05:46:10 +00001158; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
1159; X64-NEXT: vmovdqa %xmm1, -{{[0-9]+}}(%rsp)
1160; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001161entry:
1162 %__a.addr.i = alloca <2 x i64>, align 16
1163 %__b.addr.i = alloca <2 x i64>, align 16
1164 %vCr = alloca <2 x i64>, align 16
1165 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001166 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
1167 %tmp2 = load i16, i16* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001168 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
1169 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
1170 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
1171 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
1172 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
1173 ret void
1174}
1175
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001176define void @isel_crash_16w(i16* %cV_R.addr) {
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001177; X32-LABEL: isel_crash_16w:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001178; X32: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001179; X32-NEXT: pushl %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001180; X32-NEXT: .cfi_def_cfa_offset 8
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001181; X32-NEXT: .cfi_offset %ebp, -8
1182; X32-NEXT: movl %esp, %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001183; X32-NEXT: .cfi_def_cfa_register %ebp
1184; X32-NEXT: andl $-32, %esp
1185; X32-NEXT: subl $128, %esp
1186; X32-NEXT: movl 8(%ebp), %eax
1187; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1188; X32-NEXT: vmovaps %ymm0, (%esp)
1189; X32-NEXT: vpbroadcastw (%eax), %ymm1
1190; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
1191; X32-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%esp)
1192; X32-NEXT: movl %ebp, %esp
1193; X32-NEXT: popl %ebp
1194; X32-NEXT: vzeroupper
1195; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001196;
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001197; X64-LABEL: isel_crash_16w:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001198; X64: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001199; X64-NEXT: pushq %rbp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001200; X64-NEXT: .cfi_def_cfa_offset 16
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001201; X64-NEXT: .cfi_offset %rbp, -16
1202; X64-NEXT: movq %rsp, %rbp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001203; X64-NEXT: .cfi_def_cfa_register %rbp
1204; X64-NEXT: andq $-32, %rsp
1205; X64-NEXT: subq $128, %rsp
1206; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1207; X64-NEXT: vmovaps %ymm0, (%rsp)
Nirav Dave3264c1b2018-03-19 20:19:46 +00001208; X64-NEXT: vpbroadcastw (%rdi), %ymm1
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001209; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
1210; X64-NEXT: vmovdqa %ymm1, {{[0-9]+}}(%rsp)
1211; X64-NEXT: movq %rbp, %rsp
1212; X64-NEXT: popq %rbp
1213; X64-NEXT: vzeroupper
1214; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001215eintry:
1216 %__a.addr.i = alloca <4 x i64>, align 16
1217 %__b.addr.i = alloca <4 x i64>, align 16
1218 %vCr = alloca <4 x i64>, align 16
1219 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001220 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
1221 %tmp2 = load i16, i16* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001222 %splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0
1223 %splat.splat = shufflevector <16 x i16> %splat.splatinsert, <16 x i16> undef, <16 x i32> zeroinitializer
1224 %tmp3 = bitcast <16 x i16> %splat.splat to <4 x i64>
1225 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
1226 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
1227 ret void
1228}
1229
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001230define void @isel_crash_4d(i32* %cV_R.addr) {
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001231; X32-LABEL: isel_crash_4d:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001232; X32: ## %bb.0: ## %entry
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001233; X32-NEXT: subl $60, %esp
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001234; X32-NEXT: .cfi_def_cfa_offset 64
1235; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1236; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1237; X32-NEXT: vmovaps %xmm0, (%esp)
1238; X32-NEXT: vbroadcastss (%eax), %xmm1
1239; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
1240; X32-NEXT: vmovaps %xmm1, {{[0-9]+}}(%esp)
1241; X32-NEXT: addl $60, %esp
1242; X32-NEXT: retl
1243;
Nirav Dave3264c1b2018-03-19 20:19:46 +00001244; X64-LABEL: isel_crash_4d:
1245; X64: ## %bb.0: ## %entry
1246; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1247; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
1248; X64-NEXT: vbroadcastss (%rdi), %xmm1
1249; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
1250; X64-NEXT: vmovaps %xmm1, -{{[0-9]+}}(%rsp)
1251; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001252entry:
1253 %__a.addr.i = alloca <2 x i64>, align 16
1254 %__b.addr.i = alloca <2 x i64>, align 16
1255 %vCr = alloca <2 x i64>, align 16
1256 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001257 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
1258 %tmp2 = load i32, i32* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001259 %splat.splatinsert = insertelement <4 x i32> undef, i32 %tmp2, i32 0
1260 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1261 %tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64>
1262 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
1263 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
1264 ret void
1265}
1266
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001267define void @isel_crash_8d(i32* %cV_R.addr) {
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001268; X32-LABEL: isel_crash_8d:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001269; X32: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001270; X32-NEXT: pushl %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001271; X32-NEXT: .cfi_def_cfa_offset 8
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001272; X32-NEXT: .cfi_offset %ebp, -8
1273; X32-NEXT: movl %esp, %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001274; X32-NEXT: .cfi_def_cfa_register %ebp
1275; X32-NEXT: andl $-32, %esp
1276; X32-NEXT: subl $128, %esp
1277; X32-NEXT: movl 8(%ebp), %eax
1278; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1279; X32-NEXT: vmovaps %ymm0, (%esp)
1280; X32-NEXT: vbroadcastss (%eax), %ymm1
1281; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
1282; X32-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
1283; X32-NEXT: movl %ebp, %esp
1284; X32-NEXT: popl %ebp
1285; X32-NEXT: vzeroupper
1286; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001287;
Nirav Dave3264c1b2018-03-19 20:19:46 +00001288; X64-LABEL: isel_crash_8d:
1289; X64: ## %bb.0: ## %eintry
1290; X64-NEXT: pushq %rbp
1291; X64-NEXT: .cfi_def_cfa_offset 16
1292; X64-NEXT: .cfi_offset %rbp, -16
1293; X64-NEXT: movq %rsp, %rbp
1294; X64-NEXT: .cfi_def_cfa_register %rbp
1295; X64-NEXT: andq $-32, %rsp
1296; X64-NEXT: subq $128, %rsp
1297; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1298; X64-NEXT: vmovaps %ymm0, (%rsp)
1299; X64-NEXT: vbroadcastss (%rdi), %ymm1
1300; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
1301; X64-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
1302; X64-NEXT: movq %rbp, %rsp
1303; X64-NEXT: popq %rbp
1304; X64-NEXT: vzeroupper
1305; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001306eintry:
1307 %__a.addr.i = alloca <4 x i64>, align 16
1308 %__b.addr.i = alloca <4 x i64>, align 16
1309 %vCr = alloca <4 x i64>, align 16
1310 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001311 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
1312 %tmp2 = load i32, i32* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001313 %splat.splatinsert = insertelement <8 x i32> undef, i32 %tmp2, i32 0
1314 %splat.splat = shufflevector <8 x i32> %splat.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
1315 %tmp3 = bitcast <8 x i32> %splat.splat to <4 x i64>
1316 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
1317 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
1318 ret void
1319}
1320
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001321define void @isel_crash_2q(i64* %cV_R.addr) {
Craig Topper15d116a2017-01-03 05:46:10 +00001322; X32-LABEL: isel_crash_2q:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001323; X32: ## %bb.0: ## %entry
Craig Topper15d116a2017-01-03 05:46:10 +00001324; X32-NEXT: subl $60, %esp
Craig Topper15d116a2017-01-03 05:46:10 +00001325; X32-NEXT: .cfi_def_cfa_offset 64
1326; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
1327; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1328; X32-NEXT: vmovaps %xmm0, (%esp)
Simon Pilgrime95550f2019-02-01 21:41:30 +00001329; X32-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
Craig Topper15d116a2017-01-03 05:46:10 +00001330; X32-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
Simon Pilgrime95550f2019-02-01 21:41:30 +00001331; X32-NEXT: vmovaps %xmm1, {{[0-9]+}}(%esp)
Craig Topper15d116a2017-01-03 05:46:10 +00001332; X32-NEXT: addl $60, %esp
1333; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001334;
Nirav Dave3264c1b2018-03-19 20:19:46 +00001335; X64-LABEL: isel_crash_2q:
1336; X64: ## %bb.0: ## %entry
1337; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1338; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
Simon Pilgrime95550f2019-02-01 21:41:30 +00001339; X64-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0]
Nirav Dave3264c1b2018-03-19 20:19:46 +00001340; X64-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
Simon Pilgrime95550f2019-02-01 21:41:30 +00001341; X64-NEXT: vmovaps %xmm1, -{{[0-9]+}}(%rsp)
Nirav Dave3264c1b2018-03-19 20:19:46 +00001342; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001343entry:
1344 %__a.addr.i = alloca <2 x i64>, align 16
1345 %__b.addr.i = alloca <2 x i64>, align 16
1346 %vCr = alloca <2 x i64>, align 16
1347 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001348 %tmp = load <2 x i64>, <2 x i64>* %vCr, align 16
1349 %tmp2 = load i64, i64* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001350 %splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0
1351 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
1352 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
1353 store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
1354 ret void
1355}
1356
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001357define void @isel_crash_4q(i64* %cV_R.addr) {
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001358; X32-LABEL: isel_crash_4q:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +00001359; X32: ## %bb.0: ## %eintry
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001360; X32-NEXT: pushl %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001361; X32-NEXT: .cfi_def_cfa_offset 8
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001362; X32-NEXT: .cfi_offset %ebp, -8
1363; X32-NEXT: movl %esp, %ebp
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001364; X32-NEXT: .cfi_def_cfa_register %ebp
1365; X32-NEXT: andl $-32, %esp
1366; X32-NEXT: subl $128, %esp
1367; X32-NEXT: movl 8(%ebp), %eax
1368; X32-NEXT: vxorps %xmm0, %xmm0, %xmm0
1369; X32-NEXT: vmovaps %ymm0, (%esp)
Simon Pilgrim952abce2019-02-19 15:57:09 +00001370; X32-NEXT: vbroadcastsd (%eax), %ymm1
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001371; X32-NEXT: vmovaps %ymm0, {{[0-9]+}}(%esp)
Craig Topperb70ca502018-01-17 18:58:22 +00001372; X32-NEXT: vmovaps %ymm1, {{[0-9]+}}(%esp)
Dinar Temirbulatova0beede2017-08-03 08:50:18 +00001373; X32-NEXT: movl %ebp, %esp
1374; X32-NEXT: popl %ebp
1375; X32-NEXT: vzeroupper
1376; X32-NEXT: retl
Craig Topper7eb0e7c2016-09-29 05:54:43 +00001377;
Nirav Dave3264c1b2018-03-19 20:19:46 +00001378; X64-LABEL: isel_crash_4q:
1379; X64: ## %bb.0: ## %eintry
1380; X64-NEXT: pushq %rbp
1381; X64-NEXT: .cfi_def_cfa_offset 16
1382; X64-NEXT: .cfi_offset %rbp, -16
1383; X64-NEXT: movq %rsp, %rbp
1384; X64-NEXT: .cfi_def_cfa_register %rbp
1385; X64-NEXT: andq $-32, %rsp
1386; X64-NEXT: subq $128, %rsp
1387; X64-NEXT: vxorps %xmm0, %xmm0, %xmm0
1388; X64-NEXT: vmovaps %ymm0, (%rsp)
1389; X64-NEXT: vbroadcastsd (%rdi), %ymm1
1390; X64-NEXT: vmovaps %ymm0, {{[0-9]+}}(%rsp)
1391; X64-NEXT: vmovaps %ymm1, {{[0-9]+}}(%rsp)
1392; X64-NEXT: movq %rbp, %rsp
1393; X64-NEXT: popq %rbp
1394; X64-NEXT: vzeroupper
1395; X64-NEXT: retq
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001396eintry:
1397 %__a.addr.i = alloca <4 x i64>, align 16
1398 %__b.addr.i = alloca <4 x i64>, align 16
1399 %vCr = alloca <4 x i64>, align 16
1400 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
David Blaikiea79ac142015-02-27 21:17:42 +00001401 %tmp = load <4 x i64>, <4 x i64>* %vCr, align 16
1402 %tmp2 = load i64, i64* %cV_R.addr, align 4
Quentin Colombet2d5c1562014-03-24 17:54:19 +00001403 %splat.splatinsert = insertelement <4 x i64> undef, i64 %tmp2, i32 0
1404 %splat.splat = shufflevector <4 x i64> %splat.splatinsert, <4 x i64> undef, <4 x i32> zeroinitializer
1405 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
1406 store <4 x i64> %splat.splat, <4 x i64>* %__b.addr.i, align 16
1407 ret void
1408}