blob: 83100a8691f8c0bc913ab01ae3ad3f425fb2a8e3 [file] [log] [blame]
Nadav Rotem1ec141d2011-11-18 02:49:55 +00001; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
2
3; CHECK: vpbroadcastb (%
4define <16 x i8> @BB16(i8* %ptr) nounwind uwtable readnone ssp {
5entry:
6 %q = load i8* %ptr, align 4
7 %q0 = insertelement <16 x i8> undef, i8 %q, i32 0
8 %q1 = insertelement <16 x i8> %q0, i8 %q, i32 1
9 %q2 = insertelement <16 x i8> %q1, i8 %q, i32 2
10 %q3 = insertelement <16 x i8> %q2, i8 %q, i32 3
11 %q4 = insertelement <16 x i8> %q3, i8 %q, i32 4
12 %q5 = insertelement <16 x i8> %q4, i8 %q, i32 5
13 %q6 = insertelement <16 x i8> %q5, i8 %q, i32 6
14 %q7 = insertelement <16 x i8> %q6, i8 %q, i32 7
15 %q8 = insertelement <16 x i8> %q7, i8 %q, i32 8
16 %q9 = insertelement <16 x i8> %q8, i8 %q, i32 9
17 %qa = insertelement <16 x i8> %q9, i8 %q, i32 10
18 %qb = insertelement <16 x i8> %qa, i8 %q, i32 11
19 %qc = insertelement <16 x i8> %qb, i8 %q, i32 12
20 %qd = insertelement <16 x i8> %qc, i8 %q, i32 13
21 %qe = insertelement <16 x i8> %qd, i8 %q, i32 14
22 %qf = insertelement <16 x i8> %qe, i8 %q, i32 15
23 ret <16 x i8> %qf
24}
25; CHECK: vpbroadcastb (%
26define <32 x i8> @BB32(i8* %ptr) nounwind uwtable readnone ssp {
27entry:
28 %q = load i8* %ptr, align 4
29 %q0 = insertelement <32 x i8> undef, i8 %q, i32 0
30 %q1 = insertelement <32 x i8> %q0, i8 %q, i32 1
31 %q2 = insertelement <32 x i8> %q1, i8 %q, i32 2
32 %q3 = insertelement <32 x i8> %q2, i8 %q, i32 3
33 %q4 = insertelement <32 x i8> %q3, i8 %q, i32 4
34 %q5 = insertelement <32 x i8> %q4, i8 %q, i32 5
35 %q6 = insertelement <32 x i8> %q5, i8 %q, i32 6
36 %q7 = insertelement <32 x i8> %q6, i8 %q, i32 7
37 %q8 = insertelement <32 x i8> %q7, i8 %q, i32 8
38 %q9 = insertelement <32 x i8> %q8, i8 %q, i32 9
39 %qa = insertelement <32 x i8> %q9, i8 %q, i32 10
40 %qb = insertelement <32 x i8> %qa, i8 %q, i32 11
41 %qc = insertelement <32 x i8> %qb, i8 %q, i32 12
42 %qd = insertelement <32 x i8> %qc, i8 %q, i32 13
43 %qe = insertelement <32 x i8> %qd, i8 %q, i32 14
44 %qf = insertelement <32 x i8> %qe, i8 %q, i32 15
45
46 %q20 = insertelement <32 x i8> %qf, i8 %q, i32 16
47 %q21 = insertelement <32 x i8> %q20, i8 %q, i32 17
48 %q22 = insertelement <32 x i8> %q21, i8 %q, i32 18
49 %q23 = insertelement <32 x i8> %q22, i8 %q, i32 19
50 %q24 = insertelement <32 x i8> %q23, i8 %q, i32 20
51 %q25 = insertelement <32 x i8> %q24, i8 %q, i32 21
52 %q26 = insertelement <32 x i8> %q25, i8 %q, i32 22
53 %q27 = insertelement <32 x i8> %q26, i8 %q, i32 23
54 %q28 = insertelement <32 x i8> %q27, i8 %q, i32 24
55 %q29 = insertelement <32 x i8> %q28, i8 %q, i32 25
56 %q2a = insertelement <32 x i8> %q29, i8 %q, i32 26
57 %q2b = insertelement <32 x i8> %q2a, i8 %q, i32 27
58 %q2c = insertelement <32 x i8> %q2b, i8 %q, i32 28
59 %q2d = insertelement <32 x i8> %q2c, i8 %q, i32 29
60 %q2e = insertelement <32 x i8> %q2d, i8 %q, i32 30
61 %q2f = insertelement <32 x i8> %q2e, i8 %q, i32 31
62 ret <32 x i8> %q2f
63}
64; CHECK: vpbroadcastw (%
65
66define <8 x i16> @W16(i16* %ptr) nounwind uwtable readnone ssp {
67entry:
68 %q = load i16* %ptr, align 4
69 %q0 = insertelement <8 x i16> undef, i16 %q, i32 0
70 %q1 = insertelement <8 x i16> %q0, i16 %q, i32 1
71 %q2 = insertelement <8 x i16> %q1, i16 %q, i32 2
72 %q3 = insertelement <8 x i16> %q2, i16 %q, i32 3
73 %q4 = insertelement <8 x i16> %q3, i16 %q, i32 4
74 %q5 = insertelement <8 x i16> %q4, i16 %q, i32 5
75 %q6 = insertelement <8 x i16> %q5, i16 %q, i32 6
76 %q7 = insertelement <8 x i16> %q6, i16 %q, i32 7
77 ret <8 x i16> %q7
78}
79; CHECK: vpbroadcastw (%
80define <16 x i16> @WW16(i16* %ptr) nounwind uwtable readnone ssp {
81entry:
82 %q = load i16* %ptr, align 4
83 %q0 = insertelement <16 x i16> undef, i16 %q, i32 0
84 %q1 = insertelement <16 x i16> %q0, i16 %q, i32 1
85 %q2 = insertelement <16 x i16> %q1, i16 %q, i32 2
86 %q3 = insertelement <16 x i16> %q2, i16 %q, i32 3
87 %q4 = insertelement <16 x i16> %q3, i16 %q, i32 4
88 %q5 = insertelement <16 x i16> %q4, i16 %q, i32 5
89 %q6 = insertelement <16 x i16> %q5, i16 %q, i32 6
90 %q7 = insertelement <16 x i16> %q6, i16 %q, i32 7
91 %q8 = insertelement <16 x i16> %q7, i16 %q, i32 8
92 %q9 = insertelement <16 x i16> %q8, i16 %q, i32 9
93 %qa = insertelement <16 x i16> %q9, i16 %q, i32 10
94 %qb = insertelement <16 x i16> %qa, i16 %q, i32 11
95 %qc = insertelement <16 x i16> %qb, i16 %q, i32 12
96 %qd = insertelement <16 x i16> %qc, i16 %q, i32 13
97 %qe = insertelement <16 x i16> %qd, i16 %q, i32 14
98 %qf = insertelement <16 x i16> %qe, i16 %q, i32 15
99 ret <16 x i16> %qf
100}
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000101; CHECK: vbroadcastss (%
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000102define <4 x i32> @D32(i32* %ptr) nounwind uwtable readnone ssp {
103entry:
104 %q = load i32* %ptr, align 4
105 %q0 = insertelement <4 x i32> undef, i32 %q, i32 0
106 %q1 = insertelement <4 x i32> %q0, i32 %q, i32 1
107 %q2 = insertelement <4 x i32> %q1, i32 %q, i32 2
108 %q3 = insertelement <4 x i32> %q2, i32 %q, i32 3
109 ret <4 x i32> %q3
110}
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000111; CHECK: vbroadcastss (%
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000112define <8 x i32> @DD32(i32* %ptr) nounwind uwtable readnone ssp {
113entry:
114 %q = load i32* %ptr, align 4
115 %q0 = insertelement <8 x i32> undef, i32 %q, i32 0
116 %q1 = insertelement <8 x i32> %q0, i32 %q, i32 1
117 %q2 = insertelement <8 x i32> %q1, i32 %q, i32 2
118 %q3 = insertelement <8 x i32> %q2, i32 %q, i32 3
119 %q4 = insertelement <8 x i32> %q3, i32 %q, i32 4
120 %q5 = insertelement <8 x i32> %q4, i32 %q, i32 5
121 %q6 = insertelement <8 x i32> %q5, i32 %q, i32 6
122 %q7 = insertelement <8 x i32> %q6, i32 %q, i32 7
123 ret <8 x i32> %q7
124}
125; CHECK: vpbroadcastq (%
126define <2 x i64> @Q64(i64* %ptr) nounwind uwtable readnone ssp {
127entry:
128 %q = load i64* %ptr, align 4
129 %q0 = insertelement <2 x i64> undef, i64 %q, i32 0
130 %q1 = insertelement <2 x i64> %q0, i64 %q, i32 1
131 ret <2 x i64> %q1
132}
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000133; CHECK: vbroadcastsd (%
Nadav Rotem1ec141d2011-11-18 02:49:55 +0000134define <4 x i64> @QQ64(i64* %ptr) nounwind uwtable readnone ssp {
135entry:
136 %q = load i64* %ptr, align 4
137 %q0 = insertelement <4 x i64> undef, i64 %q, i32 0
138 %q1 = insertelement <4 x i64> %q0, i64 %q, i32 1
139 %q2 = insertelement <4 x i64> %q1, i64 %q, i32 2
140 %q3 = insertelement <4 x i64> %q2, i64 %q, i32 3
141 ret <4 x i64> %q3
142}
Craig Topper430f3f12012-01-10 08:23:59 +0000143
144; make sure that we still don't support broadcast double into 128-bit vector
145; this used to crash
146define <2 x double> @I(double* %ptr) nounwind uwtable readnone ssp {
147entry:
148 %q = load double* %ptr, align 4
149 %vecinit.i = insertelement <2 x double> undef, double %q, i32 0
150 %vecinit2.i = insertelement <2 x double> %vecinit.i, double %q, i32 1
151 ret <2 x double> %vecinit2.i
152}
Nadav Rotem82609df2012-04-08 12:54:54 +0000153
154; CHECK: V111
155; CHECK: vpbroadcastd
156; CHECK: ret
157define <8 x i32> @V111(<8 x i32> %in) nounwind uwtable readnone ssp {
158entry:
159 %g = add <8 x i32> %in, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
160 ret <8 x i32> %g
161}
162
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000163; CHECK: V113
164; CHECK: vbroadcastss
165; CHECK: ret
166define <8 x float> @V113(<8 x float> %in) nounwind uwtable readnone ssp {
167entry:
168 %g = fadd <8 x float> %in, <float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000, float 0xbf80000000000000>
169 ret <8 x float> %g
170}
171
Nadav Rotem82609df2012-04-08 12:54:54 +0000172; CHECK: _e2
173; CHECK: vbroadcastss
174; CHECK: ret
175define <4 x float> @_e2(float* %ptr) nounwind uwtable readnone ssp {
176 %vecinit.i = insertelement <4 x float> undef, float 0xbf80000000000000, i32 0
177 %vecinit2.i = insertelement <4 x float> %vecinit.i, float 0xbf80000000000000, i32 1
178 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float 0xbf80000000000000, i32 2
179 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float 0xbf80000000000000, i32 3
180 ret <4 x float> %vecinit6.i
181}
182
Nadav Rotemb801ca32012-04-09 07:45:58 +0000183; CHECK: _e4
184; CHECK-NOT: broadcast
185; CHECK: ret
186define <8 x i8> @_e4(i8* %ptr) nounwind uwtable readnone ssp {
187 %vecinit0.i = insertelement <8 x i8> undef, i8 52, i32 0
188 %vecinit1.i = insertelement <8 x i8> %vecinit0.i, i8 52, i32 1
189 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 52, i32 2
190 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 52, i32 3
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000191 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 52, i32 4
192 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 52, i32 5
193 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 52, i32 6
194 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 52, i32 7
Nadav Rotemb801ca32012-04-09 07:45:58 +0000195 ret <8 x i8> %vecinit7.i
196}
Nadav Rotemaa3ff8d2012-04-24 11:07:03 +0000197
198
199define void @crash() nounwind alwaysinline {
200WGLoopsEntry:
201 br i1 undef, label %ret, label %footer329VF
202
203footer329VF:
204 %A.0.inVF = fmul float undef, 6.553600e+04
205 %B.0.in407VF = fmul <8 x float> undef, <float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04, float 6.553600e+04>
206 %A.0VF = fptosi float %A.0.inVF to i32
207 %B.0408VF = fptosi <8 x float> %B.0.in407VF to <8 x i32>
208 %0 = and <8 x i32> %B.0408VF, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
209 %1 = and i32 %A.0VF, 65535
210 %temp1098VF = insertelement <8 x i32> undef, i32 %1, i32 0
211 %vector1099VF = shufflevector <8 x i32> %temp1098VF, <8 x i32> undef, <8 x i32> zeroinitializer
212 br i1 undef, label %preload1201VF, label %footer349VF
213
214preload1201VF:
215 br label %footer349VF
216
217footer349VF:
218 %2 = mul nsw <8 x i32> undef, %0
219 %3 = mul nsw <8 x i32> undef, %vector1099VF
220 br label %footer329VF
221
222ret:
223 ret void
224}
Nadav Rotem900c7cb2012-05-19 19:57:37 +0000225
226; CHECK: _inreg0
227; CHECK: broadcastss
228; CHECK: ret
229define <8 x i32> @_inreg0(i32 %scalar) nounwind uwtable readnone ssp {
230 %in = insertelement <8 x i32> undef, i32 %scalar, i32 0
231 %wide = shufflevector <8 x i32> %in, <8 x i32> undef, <8 x i32> zeroinitializer
232 ret <8 x i32> %wide
233}
234
235; CHECK: _inreg1
236; CHECK: broadcastss
237; CHECK: ret
238define <8 x float> @_inreg1(float %scalar) nounwind uwtable readnone ssp {
239 %in = insertelement <8 x float> undef, float %scalar, i32 0
240 %wide = shufflevector <8 x float> %in, <8 x float> undef, <8 x i32> zeroinitializer
241 ret <8 x float> %wide
242}
243
244; CHECK: _inreg2
245; CHECK: broadcastss
246; CHECK: ret
247define <4 x float> @_inreg2(float %scalar) nounwind uwtable readnone ssp {
248 %in = insertelement <4 x float> undef, float %scalar, i32 0
249 %wide = shufflevector <4 x float> %in, <4 x float> undef, <4 x i32> zeroinitializer
250 ret <4 x float> %wide
251}
252
253; CHECK: _inreg3
254; CHECK: broadcastsd
255; CHECK: ret
256define <4 x double> @_inreg3(double %scalar) nounwind uwtable readnone ssp {
257 %in = insertelement <4 x double> undef, double %scalar, i32 0
258 %wide = shufflevector <4 x double> %in, <4 x double> undef, <4 x i32> zeroinitializer
259 ret <4 x double> %wide
260}
261
Stephen Lin6f36b452013-07-18 22:47:09 +0000262;CHECK-LABEL: _inreg8xfloat:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000263;CHECK: vbroadcastss
264;CHECK: ret
265define <8 x float> @_inreg8xfloat(<8 x float> %a) {
266 %b = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> zeroinitializer
267 ret <8 x float> %b
268}
269
Stephen Lin6f36b452013-07-18 22:47:09 +0000270;CHECK-LABEL: _inreg4xfloat:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000271;CHECK: vbroadcastss
272;CHECK: ret
273define <4 x float> @_inreg4xfloat(<4 x float> %a) {
274 %b = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> zeroinitializer
275 ret <4 x float> %b
276}
277
Stephen Lin6f36b452013-07-18 22:47:09 +0000278;CHECK-LABEL: _inreg16xi16:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000279;CHECK: vpbroadcastw
280;CHECK: ret
281define <16 x i16> @_inreg16xi16(<16 x i16> %a) {
282 %b = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> zeroinitializer
283 ret <16 x i16> %b
284}
285
Stephen Lin6f36b452013-07-18 22:47:09 +0000286;CHECK-LABEL: _inreg8xi16:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000287;CHECK: vpbroadcastw
288;CHECK: ret
289define <8 x i16> @_inreg8xi16(<8 x i16> %a) {
290 %b = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> zeroinitializer
291 ret <8 x i16> %b
292}
293
294
Stephen Lin6f36b452013-07-18 22:47:09 +0000295;CHECK-LABEL: _inreg4xi64:
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000296;CHECK: vbroadcastsd
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000297;CHECK: ret
298define <4 x i64> @_inreg4xi64(<4 x i64> %a) {
299 %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
300 ret <4 x i64> %b
301}
302
Stephen Lin6f36b452013-07-18 22:47:09 +0000303;CHECK-LABEL: _inreg2xi64:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000304;CHECK: vpbroadcastq
305;CHECK: ret
306define <2 x i64> @_inreg2xi64(<2 x i64> %a) {
307 %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
308 ret <2 x i64> %b
309}
310
Stephen Lin6f36b452013-07-18 22:47:09 +0000311;CHECK-LABEL: _inreg4xdouble:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000312;CHECK: vbroadcastsd
313;CHECK: ret
314define <4 x double> @_inreg4xdouble(<4 x double> %a) {
315 %b = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> zeroinitializer
316 ret <4 x double> %b
Simon Pilgrim106abe42015-01-26 21:28:32 +0000317}
318
319;CHECK-LABEL: _inreg2xdouble:
320;CHECK: vmovddup
321;CHECK: ret
322define <2 x double> @_inreg2xdouble(<2 x double> %a) {
323 %b = shufflevector <2 x double> %a, <2 x double> undef, <2 x i32> zeroinitializer
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000324 ret <2 x double> %b
325}
326
Stephen Lin6f36b452013-07-18 22:47:09 +0000327;CHECK-LABEL: _inreg8xi32:
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000328;CHECK: vbroadcastss
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000329;CHECK: ret
330define <8 x i32> @_inreg8xi32(<8 x i32> %a) {
331 %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
332 ret <8 x i32> %b
333}
334
Stephen Lin6f36b452013-07-18 22:47:09 +0000335;CHECK-LABEL: _inreg4xi32:
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000336;CHECK: vbroadcastss
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000337;CHECK: ret
338define <4 x i32> @_inreg4xi32(<4 x i32> %a) {
339 %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
340 ret <4 x i32> %b
341}
342
Stephen Lin6f36b452013-07-18 22:47:09 +0000343;CHECK-LABEL: _inreg32xi8:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000344;CHECK: vpbroadcastb
345;CHECK: ret
346define <32 x i8> @_inreg32xi8(<32 x i8> %a) {
347 %b = shufflevector <32 x i8> %a, <32 x i8> undef, <32 x i32> zeroinitializer
348 ret <32 x i8> %b
349}
350
Stephen Lin6f36b452013-07-18 22:47:09 +0000351;CHECK-LABEL: _inreg16xi8:
Elena Demikhovsky9af899f2012-07-01 06:12:26 +0000352;CHECK: vpbroadcastb
353;CHECK: ret
354define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
355 %b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
356 ret <16 x i8> %b
357}
Robert Lougher7d9084f2014-02-11 15:42:46 +0000358
359; These tests check that a vbroadcast instruction is used when we have a splat
360; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
361; (via the insertelements).
362
363; CHECK-LABEL: splat_concat1
364; CHECK-NOT: vinsertf128
365; CHECK: vbroadcastss
366; CHECK-NEXT: ret
367define <8 x float> @splat_concat1(float %f) {
368 %1 = insertelement <4 x float> undef, float %f, i32 0
369 %2 = insertelement <4 x float> %1, float %f, i32 1
370 %3 = insertelement <4 x float> %2, float %f, i32 2
371 %4 = insertelement <4 x float> %3, float %f, i32 3
372 %5 = shufflevector <4 x float> %4, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
373 ret <8 x float> %5
374}
375
376; CHECK-LABEL: splat_concat2
377; CHECK-NOT: vinsertf128
378; CHECK: vbroadcastss
379; CHECK-NEXT: ret
380define <8 x float> @splat_concat2(float %f) {
381 %1 = insertelement <4 x float> undef, float %f, i32 0
382 %2 = insertelement <4 x float> %1, float %f, i32 1
383 %3 = insertelement <4 x float> %2, float %f, i32 2
384 %4 = insertelement <4 x float> %3, float %f, i32 3
385 %5 = insertelement <4 x float> undef, float %f, i32 0
386 %6 = insertelement <4 x float> %5, float %f, i32 1
387 %7 = insertelement <4 x float> %6, float %f, i32 2
388 %8 = insertelement <4 x float> %7, float %f, i32 3
389 %9 = shufflevector <4 x float> %4, <4 x float> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
390 ret <8 x float> %9
391}
392
393; CHECK-LABEL: splat_concat3
394; CHECK-NOT: vinsertf128
395; CHECK: vbroadcastsd
396; CHECK-NEXT: ret
397define <4 x double> @splat_concat3(double %d) {
398 %1 = insertelement <2 x double> undef, double %d, i32 0
399 %2 = insertelement <2 x double> %1, double %d, i32 1
400 %3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
401 ret <4 x double> %3
402}
403
404; CHECK-LABEL: splat_concat4
405; CHECK-NOT: vinsertf128
406; CHECK: vbroadcastsd
407; CHECK-NEXT: ret
408define <4 x double> @splat_concat4(double %d) {
409 %1 = insertelement <2 x double> undef, double %d, i32 0
410 %2 = insertelement <2 x double> %1, double %d, i32 1
411 %3 = insertelement <2 x double> undef, double %d, i32 0
412 %4 = insertelement <2 x double> %3, double %d, i32 1
413 %5 = shufflevector <2 x double> %2, <2 x double> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
414 ret <4 x double> %5
415}
Quentin Colombet2d5c1562014-03-24 17:54:19 +0000416
417; Test cases for <rdar://problem/16074331>.
418; Instruction selection for broacast instruction fails if
419; the load cannot be folded into the broadcast.
420; This happens if the load has initial one use but other uses are
421; created later, or if selection DAG cannot prove that folding the
422; load will not create a cycle in the DAG.
423; Those test cases exerce the latter.
424
425; CHECK-LABEL: isel_crash_16b
426; CHECK: vpbroadcastb {{[^,]+}}, %xmm{{[0-9]+}}
427; CHECK: ret
428define void @isel_crash_16b(i8* %cV_R.addr) {
429eintry:
430 %__a.addr.i = alloca <2 x i64>, align 16
431 %__b.addr.i = alloca <2 x i64>, align 16
432 %vCr = alloca <2 x i64>, align 16
433 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
434 %tmp = load <2 x i64>* %vCr, align 16
435 %tmp2 = load i8* %cV_R.addr, align 4
436 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
437 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
438 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
439 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
440 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
441 ret void
442}
443
444; CHECK-LABEL: isel_crash_32b
445; CHECK: vpbroadcastb {{[^,]+}}, %ymm{{[0-9]+}}
446; CHECK: ret
447define void @isel_crash_32b(i8* %cV_R.addr) {
448eintry:
449 %__a.addr.i = alloca <4 x i64>, align 16
450 %__b.addr.i = alloca <4 x i64>, align 16
451 %vCr = alloca <4 x i64>, align 16
452 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
453 %tmp = load <4 x i64>* %vCr, align 16
454 %tmp2 = load i8* %cV_R.addr, align 4
455 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
456 %splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitializer
457 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
458 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
459 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
460 ret void
461}
462
463; CHECK-LABEL: isel_crash_8w
464; CHECK: vpbroadcastw {{[^,]+}}, %xmm{{[0-9]+}}
465; CHECK: ret
466define void @isel_crash_8w(i16* %cV_R.addr) {
467entry:
468 %__a.addr.i = alloca <2 x i64>, align 16
469 %__b.addr.i = alloca <2 x i64>, align 16
470 %vCr = alloca <2 x i64>, align 16
471 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
472 %tmp = load <2 x i64>* %vCr, align 16
473 %tmp2 = load i16* %cV_R.addr, align 4
474 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
475 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
476 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
477 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
478 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
479 ret void
480}
481
482; CHECK-LABEL: isel_crash_16w
483; CHECK: vpbroadcastw {{[^,]+}}, %ymm{{[0-9]+}}
484; CHECK: ret
485define void @isel_crash_16w(i16* %cV_R.addr) {
486eintry:
487 %__a.addr.i = alloca <4 x i64>, align 16
488 %__b.addr.i = alloca <4 x i64>, align 16
489 %vCr = alloca <4 x i64>, align 16
490 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
491 %tmp = load <4 x i64>* %vCr, align 16
492 %tmp2 = load i16* %cV_R.addr, align 4
493 %splat.splatinsert = insertelement <16 x i16> undef, i16 %tmp2, i32 0
494 %splat.splat = shufflevector <16 x i16> %splat.splatinsert, <16 x i16> undef, <16 x i32> zeroinitializer
495 %tmp3 = bitcast <16 x i16> %splat.splat to <4 x i64>
496 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
497 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
498 ret void
499}
500
501; CHECK-LABEL: isel_crash_4d
502; CHECK: vbroadcastss {{[^,]+}}, %xmm{{[0-9]+}}
503; CHECK: ret
504define void @isel_crash_4d(i32* %cV_R.addr) {
505entry:
506 %__a.addr.i = alloca <2 x i64>, align 16
507 %__b.addr.i = alloca <2 x i64>, align 16
508 %vCr = alloca <2 x i64>, align 16
509 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
510 %tmp = load <2 x i64>* %vCr, align 16
511 %tmp2 = load i32* %cV_R.addr, align 4
512 %splat.splatinsert = insertelement <4 x i32> undef, i32 %tmp2, i32 0
513 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
514 %tmp3 = bitcast <4 x i32> %splat.splat to <2 x i64>
515 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
516 store <2 x i64> %tmp3, <2 x i64>* %__b.addr.i, align 16
517 ret void
518}
519
520; CHECK-LABEL: isel_crash_8d
521; CHECK: vbroadcastss {{[^,]+}}, %ymm{{[0-9]+}}
522; CHECK: ret
523define void @isel_crash_8d(i32* %cV_R.addr) {
524eintry:
525 %__a.addr.i = alloca <4 x i64>, align 16
526 %__b.addr.i = alloca <4 x i64>, align 16
527 %vCr = alloca <4 x i64>, align 16
528 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
529 %tmp = load <4 x i64>* %vCr, align 16
530 %tmp2 = load i32* %cV_R.addr, align 4
531 %splat.splatinsert = insertelement <8 x i32> undef, i32 %tmp2, i32 0
532 %splat.splat = shufflevector <8 x i32> %splat.splatinsert, <8 x i32> undef, <8 x i32> zeroinitializer
533 %tmp3 = bitcast <8 x i32> %splat.splat to <4 x i64>
534 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
535 store <4 x i64> %tmp3, <4 x i64>* %__b.addr.i, align 16
536 ret void
537}
538
539; CHECK-LABEL: isel_crash_2q
540; CHECK: vpbroadcastq {{[^,]+}}, %xmm{{[0-9]+}}
541; CHECK: ret
542define void @isel_crash_2q(i64* %cV_R.addr) {
543entry:
544 %__a.addr.i = alloca <2 x i64>, align 16
545 %__b.addr.i = alloca <2 x i64>, align 16
546 %vCr = alloca <2 x i64>, align 16
547 store <2 x i64> zeroinitializer, <2 x i64>* %vCr, align 16
548 %tmp = load <2 x i64>* %vCr, align 16
549 %tmp2 = load i64* %cV_R.addr, align 4
550 %splat.splatinsert = insertelement <2 x i64> undef, i64 %tmp2, i32 0
551 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
552 store <2 x i64> %tmp, <2 x i64>* %__a.addr.i, align 16
553 store <2 x i64> %splat.splat, <2 x i64>* %__b.addr.i, align 16
554 ret void
555}
556
557; CHECK-LABEL: isel_crash_4q
558; CHECK: vbroadcastsd {{[^,]+}}, %ymm{{[0-9]+}}
559; CHECK: ret
560define void @isel_crash_4q(i64* %cV_R.addr) {
561eintry:
562 %__a.addr.i = alloca <4 x i64>, align 16
563 %__b.addr.i = alloca <4 x i64>, align 16
564 %vCr = alloca <4 x i64>, align 16
565 store <4 x i64> zeroinitializer, <4 x i64>* %vCr, align 16
566 %tmp = load <4 x i64>* %vCr, align 16
567 %tmp2 = load i64* %cV_R.addr, align 4
568 %splat.splatinsert = insertelement <4 x i64> undef, i64 %tmp2, i32 0
569 %splat.splat = shufflevector <4 x i64> %splat.splatinsert, <4 x i64> undef, <4 x i32> zeroinitializer
570 store <4 x i64> %tmp, <4 x i64>* %__a.addr.i, align 16
571 store <4 x i64> %splat.splat, <4 x i64>* %__b.addr.i, align 16
572 ret void
573}