llvm/test/Transforms/SLPVectorizer/X86/shl-compatible-with-add.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=icelake-server -slp-threshold=-5 < %s | FileCheck %s

define void @intrapred_luma(ptr %0, i16 %1, i32 %conv593) {
; CHECK-LABEL: define void @intrapred_luma(
; CHECK-SAME: ptr [[TMP0:%.*]], i16 [[TMP1:%.*]], i32 [[CONV593:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i16> poison, i16 [[TMP1]], i64 0
; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> poison, <2 x i32> zeroinitializer
; CHECK-NEXT:    [[TMP4:%.*]] = zext <2 x i16> [[TMP3]] to <2 x i32>
; CHECK-NEXT:    [[DOTPRE:%.*]] = load ptr, ptr [[TMP0]], align 8
; CHECK-NEXT:    [[ARRAYIDX590:%.*]] = getelementptr i8, ptr [[DOTPRE]], i64 4304
; CHECK-NEXT:    [[CONV635:%.*]] = zext i16 [[TMP1]] to i32
; CHECK-NEXT:    [[ADD633:%.*]] = add i32 [[CONV635]], 1
; CHECK-NEXT:    [[ADD636:%.*]] = add i32 [[ADD633]], [[CONV593]]
; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 1, i32 poison>
; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x i32> [[TMP5]], i32 [[ADD636]], i64 3
; CHECK-NEXT:    [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 3>
; CHECK-NEXT:    [[TMP18:%.*]] = shufflevector <4 x i32> <i32 1, i32 poison, i32 0, i32 1>, <4 x i32> [[TMP5]], <4 x i32> <i32 0, i32 4, i32 2, i32 3>
; CHECK-NEXT:    [[TMP9:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]
; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 poison, i32 poison>, i32 [[CONV593]], i64 0
; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <4 x i32> [[TMP10]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
; CHECK-NEXT:    [[TMP12:%.*]] = or <4 x i32> [[TMP9]], [[TMP11]]
; CHECK-NEXT:    [[TMP15:%.*]] = lshr <4 x i32> [[TMP12]], <i32 1, i32 2, i32 1, i32 1>
; CHECK-NEXT:    [[TMP16:%.*]] = trunc <4 x i32> [[TMP15]] to <4 x i16>
; CHECK-NEXT:    store <4 x i16> [[TMP16]], ptr [[ARRAYIDX590]], align 2
; CHECK-NEXT:    ret void
;
entry:
  %conv5952 = zext i16 %1 to i32
  %add596 = add i32 %conv5952, 1
  %add597 = or i32 %add596, %conv593
  %shr598 = lshr i32 %add597, 1
  %conv599 = trunc i32 %shr598 to i16
  %.pre = load ptr, ptr %0, align 8
  %arrayidx590 = getelementptr i8, ptr %.pre, i64 4304
  store i16 %conv599, ptr %arrayidx590, align 2
  %mul606 = shl i32 %conv5952, 1
  %add611 = or i32 %mul606, %conv593
  %shr612 = lshr i32 %add611, 2
  %conv613 = trunc i32 %shr612 to i16
  %arrayidx615 = getelementptr i8, ptr %.pre, i64 4306
  store i16 %conv613, ptr %arrayidx615, align 2
  %conv609 = zext i16 %1 to i32
  %add621 = or i32 %conv593, %conv609
  %shr622 = lshr i32 %add621, 1
  %conv623 = trunc i32 %shr622 to i16
  %arrayidx627 = getelementptr i8, ptr %.pre, i64 4308
  store i16 %conv623, ptr %arrayidx627, align 2
  %conv635 = zext i16 %1 to i32
  %add633 = add i32 %conv635, 1
  %add636 = add i32 %add633, %conv593
  %add637 = add i32 %add636, 1
  %shr638 = lshr i32 %add637, 1
  %conv639 = trunc i32 %shr638 to i16
  %arrayidx643 = getelementptr i8, ptr %.pre, i64 4310
  store i16 %conv639, ptr %arrayidx643, align 2
  ret void
}