[RISCV] Eliminate redundant materializations after register comparison (#227673) `RISCVRedundantCopyElimination` can eliminate redundant immediate materializations when a branch establishes a known immediate value, but does not handle register-register `BEQ`/`BNE` when one operand is a non-zero immediate materialized in a register. Extend the pass to recognize `ADDI` from `X0` and `QC_LI` materializations before the branch. On the equality edge, reuse that known immediate so an identical materialization in the successor can be removed. `X0` is excluded as a target register because writes to it are discarded. Tests cover `BEQ`/`BNE`, both operand orders, clobbers, `X0`, RV32/RV64, and the relevant Xqci and XAndes variants. AI tool usage: OpenAI Codex assisted with this contribution. I reviewed and take responsibility for the final changes. Assisted-by: OpenAI Codex
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