llvm/test/Transforms/SLPVectorizer/X86/non-schedulable-node-with-non-schedulable-parent.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64 < %s | FileCheck %s

define float @test() {
; CHECK-LABEL: define float @test() {
; CHECK-NEXT:  [[BB:.*:]]
; CHECK-NEXT:    [[FADD:%.*]] = fadd float 0.000000e+00, 0.000000e+00
; CHECK-NEXT:    [[LOAD:%.*]] = load float, ptr null, align 4
; CHECK-NEXT:    [[FADD2:%.*]] = fadd float 0.000000e+00, 0.000000e+00
; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> <float poison, float poison, float 0.000000e+00, float poison>, float [[FADD]], i32 3
; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float poison>, float [[LOAD]], i32 3
; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP0]]
; CHECK-NEXT:    br i1 false, label %[[BB5:.*]], label %[[BB6:.*]]
; CHECK:       [[BB5]]:
; CHECK-NEXT:    br label %[[BB8:.*]]
; CHECK:       [[BB6]]:
; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x float> poison, float [[FADD2]], i32 0
; CHECK-NEXT:    [[TMP11:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> poison, <2 x i32> <i32 poison, i32 3>
; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> [[TMP11]], <2 x i32> <i32 0, i32 3>
; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float poison, float poison>, float [[LOAD]], i32 0
; CHECK-NEXT:    [[TMP12:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT:    [[TMP7:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP12]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT:    [[TMP8:%.*]] = fdiv <4 x float> [[TMP7]], <float 1.000000e+00, float 1.000000e+00, float 0.000000e+00, float 0.000000e+00>
; CHECK-NEXT:    br label %[[BB8]]
; CHECK:       [[BB8]]:
; CHECK-NEXT:    [[TMP9:%.*]] = phi <4 x float> [ [[TMP3]], %[[BB5]] ], [ [[TMP8]], %[[BB6]] ]
; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x float> [[TMP9]], i32 3
; CHECK-NEXT:    ret float [[TMP10]]
;
bb:
  %fadd = fadd float 0.000000e+00, 0.000000e+00
  %load = load float, ptr null, align 4
  %fadd1 = fadd float %fadd, %load
  %fadd2 = fadd float 0.000000e+00, 0.000000e+00
  %fmul = fmul float 0.000000e+00, 0.000000e+00
  %fmul3 = fmul float 0.000000e+00, 0.000000e+00
  %fadd4 = fadd float %fmul3, 0.000000e+00
  br i1 false, label %bb5, label %bb6

bb5:
  br label %bb8

bb6:
  %fdiv = fdiv float %fadd1, 0.000000e+00
  %fdiv7 = fdiv float %fadd2, 0.000000e+00
  br label %bb8

bb8:
  %phi = phi float [ 0.000000e+00, %bb5 ], [ %fdiv7, %bb6 ]
  %phi9 = phi float [ %fmul, %bb5 ], [ 0.000000e+00, %bb6 ]
  %phi10 = phi float [ %fadd4, %bb5 ], [ %load, %bb6 ]
  %phi11 = phi float [ %fadd1, %bb5 ], [ %fdiv, %bb6 ]
  ret float %phi11
}