llvm/test/Transforms/SLPVectorizer/AArch64/unsigned-after-sext-node.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -mtriple=aarch64 -passes=slp-vectorizer -S -slp-threshold=-100 < %s | FileCheck %s

define i16 @test()  {
; CHECK-LABEL: define i16 @test() {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[LNOT:%.*]] = xor i1 true, true
; CHECK-NEXT:    [[LNOT_EXT:%.*]] = zext i1 [[LNOT]] to i16
; CHECK-NEXT:    [[ADD:%.*]] = add nsw i16 0, [[LNOT_EXT]]
; CHECK-NEXT:    [[LNOT5:%.*]] = xor i1 true, true
; CHECK-NEXT:    [[LNOT_EXT6:%.*]] = zext i1 [[LNOT5]] to i16
; CHECK-NEXT:    [[ADD7:%.*]] = add nsw i16 [[ADD]], [[LNOT_EXT6]]
; CHECK-NEXT:    ret i16 [[ADD7]]
;
entry:
  %conv = sext i16 1 to i32
  %cmp = icmp eq i32 %conv, 1
  %lnot = xor i1 %cmp, true
  %lnot.ext = zext i1 %lnot to i16
  %add = add nsw i16 0, %lnot.ext
  %conv2 = sext i16 1 to i32
  %cmp3 = icmp eq i32 %conv2, 1
  %lnot5 = xor i1 %cmp3, true
  %lnot.ext6 = zext i1 %lnot5 to i16
  %add7 = add nsw i16 %add, %lnot.ext6
  ret i16 %add7
}