llvm/test/Transforms/SLPVectorizer/AArch64/external-use-icmp.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64 -slp-threshold=-20 -slp-vectorize-hor=0 < %s | FileCheck %s

define i16 @foo(i16 %in1, i16 %in2) {
; CHECK-LABEL: define i16 @foo(
; CHECK-SAME: i16 [[IN1:%.*]], i16 [[IN2:%.*]]) {
; CHECK-NEXT:  entry:
; CHECK-NEXT:    [[ZEXT1_1:%.*]] = zext i16 [[IN1]] to i64
; CHECK-NEXT:    [[ZEXT2_1:%.*]] = zext i16 [[IN2]] to i64
; CHECK-NEXT:    [[TMP10:%.*]] = mul nuw nsw i64 [[ZEXT2_1]], [[ZEXT1_1]]
; CHECK-NEXT:    [[AND1:%.*]] = and i64 [[TMP10]], 65535
; CHECK-NEXT:    [[TMP8:%.*]] = icmp ne i64 [[AND1]], 65533
; CHECK-NEXT:    [[ZEXT3_1:%.*]] = zext i1 [[TMP8]] to i16
; CHECK-NEXT:    [[CMP2_1:%.*]] = icmp ne i64 [[TMP10]], 196605
; CHECK-NEXT:    [[ZEXT4_1:%.*]] = zext i1 [[CMP2_1]] to i16
; CHECK-NEXT:    [[ADD1:%.*]] = add nuw nsw i16 [[ZEXT3_1]], [[ZEXT4_1]]
; CHECK-NEXT:    [[ZEXT1_2:%.*]] = zext i16 [[IN1]] to i64
; CHECK-NEXT:    [[ZEXT2_2:%.*]] = zext i16 [[IN2]] to i64
; CHECK-NEXT:    [[TMP13:%.*]] = mul nuw nsw i64 [[ZEXT2_2]], [[ZEXT1_2]]
; CHECK-NEXT:    [[AND2:%.*]] = and i64 [[TMP13]], 65535
; CHECK-NEXT:    [[TMP11:%.*]] = icmp ne i64 [[AND2]], 65533
; CHECK-NEXT:    [[ZEXT3_2:%.*]] = zext i1 [[TMP11]] to i16
; CHECK-NEXT:    [[CMP2_2:%.*]] = icmp ne i64 [[TMP13]], 196605
; CHECK-NEXT:    [[ZEXT4_2:%.*]] = zext i1 [[CMP2_2]] to i16
; CHECK-NEXT:    [[ADD2:%.*]] = add nuw nsw i16 [[ADD1]], [[ZEXT4_2]]
; CHECK-NEXT:    [[ADD3:%.*]] = add nuw nsw i16 [[ADD2]], [[ZEXT3_2]]
; CHECK-NEXT:    ret i16 [[ADD3]]
;
entry:
  %zext1_1 = zext i16 %in1 to i64
  %zext2_1 = zext i16 %in2 to i64
  %mul1 = mul nuw nsw i64 %zext2_1, %zext1_1
  %and1 = and i64 %mul1, 65535
  %cmp1_1 = icmp ne i64 %and1, 65533
  %zext3_1 = zext i1 %cmp1_1 to i16
  %cmp2_1 = icmp ne i64 %mul1, 196605
  %zext4_1 = zext i1 %cmp2_1 to i16
  %add1 = add nuw nsw i16 %zext3_1, %zext4_1
  %zext1_2 = zext i16 %in1 to i64
  %zext2_2 = zext i16 %in2 to i64
  %mul2 = mul nuw nsw i64 %zext2_2, %zext1_2
  %and2 = and i64 %mul2, 65535
  %cmp1_2 = icmp ne i64 %and2, 65533
  %zext3_2 = zext i1 %cmp1_2 to i16
  %cmp2_2 = icmp ne i64 %mul2, 196605
  %zext4_2 = zext i1 %cmp2_2 to i16
  %add2 = add nuw nsw i16 %add1, %zext4_2
  %add3 = add nuw nsw i16 %add2, %zext3_2
  ret i16 %add3
}