| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6 |
| ; RUN: opt -passes=loop-vectorize -force-vector-width=2 -force-vector-interleave=4 -S %s | FileCheck %s |
| |
| define i64 @bounded_load_multi_exit(ptr %src, i64 %x, i64 %N) { |
| ; CHECK-LABEL: define i64 @bounded_load_multi_exit( |
| ; CHECK-SAME: ptr [[SRC:%.*]], i64 [[X:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: [[ENTRY:.*]]: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], -1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = freeze i64 [[TMP0]] |
| ; CHECK-NEXT: [[UMIN1:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[X]]) |
| ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[UMIN1]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP2]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]] |
| ; CHECK: [[VECTOR_SCEVCHECK]]: |
| ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[N]], -1 |
| ; CHECK-NEXT: [[TMP4:%.*]] = freeze i64 [[TMP3]] |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[X]]) |
| ; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[UMIN]] to i1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]] |
| ; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]] |
| ; CHECK: [[VECTOR_PH]]: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i64 8, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[TMP9]] |
| ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] |
| ; CHECK: [[VECTOR_BODY]]: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i8> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI2:%.*]] = phi <2 x i8> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi <2 x i8> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI4:%.*]] = phi <2 x i8> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP10]] |
| ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP11]], i64 -1 |
| ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP11]], i64 -3 |
| ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP11]], i64 -5 |
| ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[TMP11]], i64 -7 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP12]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <2 x i8>, ptr [[TMP13]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <2 x i8>, ptr [[TMP14]], align 1 |
| ; CHECK-NEXT: [[WIDE_LOAD7:%.*]] = load <2 x i8>, ptr [[TMP15]], align 1 |
| ; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x i8> [[WIDE_LOAD]], <2 x i8> poison, <2 x i32> <i32 1, i32 0> |
| ; CHECK-NEXT: [[REVERSE8:%.*]] = shufflevector <2 x i8> [[WIDE_LOAD5]], <2 x i8> poison, <2 x i32> <i32 1, i32 0> |
| ; CHECK-NEXT: [[REVERSE9:%.*]] = shufflevector <2 x i8> [[WIDE_LOAD6]], <2 x i8> poison, <2 x i32> <i32 1, i32 0> |
| ; CHECK-NEXT: [[REVERSE10:%.*]] = shufflevector <2 x i8> [[WIDE_LOAD7]], <2 x i8> poison, <2 x i32> <i32 1, i32 0> |
| ; CHECK-NEXT: [[TMP16]] = xor <2 x i8> [[REVERSE]], [[VEC_PHI]] |
| ; CHECK-NEXT: [[TMP17]] = xor <2 x i8> [[REVERSE8]], [[VEC_PHI2]] |
| ; CHECK-NEXT: [[TMP18]] = xor <2 x i8> [[REVERSE9]], [[VEC_PHI3]] |
| ; CHECK-NEXT: [[TMP19]] = xor <2 x i8> [[REVERSE10]], [[VEC_PHI4]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: [[MIDDLE_BLOCK]]: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = xor <2 x i8> [[TMP17]], [[TMP16]] |
| ; CHECK-NEXT: [[BIN_RDX11:%.*]] = xor <2 x i8> [[TMP18]], [[BIN_RDX]] |
| ; CHECK-NEXT: [[BIN_RDX12:%.*]] = xor <2 x i8> [[TMP19]], [[BIN_RDX11]] |
| ; CHECK-NEXT: [[TMP21:%.*]] = call i8 @llvm.vector.reduce.xor.v2i8(<2 x i8> [[BIN_RDX12]]) |
| ; CHECK-NEXT: br label %[[SCALAR_PH]] |
| ; CHECK: [[SCALAR_PH]]: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i8 [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: br label %[[LOOP_HEADER:.*]] |
| ; CHECK: [[LOOP_HEADER]]: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ] |
| ; CHECK-NEXT: [[RED:%.*]] = phi i8 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], %[[LOOP_LATCH]] ] |
| ; CHECK-NEXT: [[IV_AND:%.*]] = and i64 [[IV]], 1 |
| ; CHECK-NEXT: [[X_INC:%.*]] = add i64 [[IV_AND]], [[X]] |
| ; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV_AND]] |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[X_INC]], 0 |
| ; CHECK-NEXT: br i1 [[CMP]], label %[[EXIT_1:.*]], label %[[LOOP_LATCH]] |
| ; CHECK: [[LOOP_LATCH]]: |
| ; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 |
| ; CHECK-NEXT: [[RED_NEXT]] = xor i8 [[L]], [[RED]] |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] |
| ; CHECK-NEXT: br i1 [[EC]], label %[[EXIT_2:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: [[EXIT_1]]: |
| ; CHECK-NEXT: [[X_INC_LCSSA:%.*]] = phi i64 [ [[X_INC]], %[[LOOP_HEADER]] ] |
| ; CHECK-NEXT: ret i64 [[X_INC_LCSSA]] |
| ; CHECK: [[EXIT_2]]: |
| ; CHECK-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i8 [ [[RED_NEXT]], %[[LOOP_LATCH]] ] |
| ; CHECK-NEXT: [[R:%.*]] = zext i8 [[RED_NEXT_LCSSA]] to i64 |
| ; CHECK-NEXT: ret i64 [[R]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %red = phi i8 [ 0, %entry ], [ %red.next, %loop.latch ] |
| %iv.and = and i64 %iv, 1 |
| %x.inc = add i64 %iv.and, %x |
| %gep.src = getelementptr i8, ptr %src, i64 %iv.and |
| %cmp = icmp eq i64 %x.inc, 0 |
| br i1 %cmp, label %exit.1, label %loop.latch |
| |
| loop.latch: |
| %l = load i8, ptr %gep.src, align 1 |
| %red.next = xor i8 %l, %red |
| %iv.next = add i64 %iv, 1 |
| %ec = icmp eq i64 %iv.next, %N |
| br i1 %ec, label %exit.2, label %loop.header |
| |
| exit.1: |
| %x.inc.lcssa = phi i64 [ %x.inc, %loop.header ] |
| ret i64 %x.inc.lcssa |
| |
| exit.2: |
| %red.next.lcssa = phi i8 [ %red.next, %loop.latch ] |
| %r = zext i8 %red.next.lcssa to i64 |
| ret i64 %r |
| } |
