llvm/test/Transforms/LoopFusion/nonadjacent_peel.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=loop-fusion -loop-fusion-peel-max-count=3 < %s | FileCheck %s

; Tests that we do not fuse these two loops together. These loops do not have
; the same tripcount, and the first loop is valid candiate for peeling; however
; the loops are not adjacent, hence they are not valid to be fused (after
; peeling).
; The expected output of this test is the function below.


@B = common global [1024 x i32] zeroinitializer, align 16

define void @function(ptr noalias %arg) {
; CHECK-LABEL: define void @function(
; CHECK-SAME: ptr noalias [[ARG:%.*]]) {
; CHECK-NEXT:  [[FOR_FIRST_PREHEADER:.*]]:
; CHECK-NEXT:    br label %[[FOR_FIRST:.*]]
; CHECK:       [[FOR_FIRST]]:
; CHECK-NEXT:    [[DOT014:%.*]] = phi i32 [ 0, %[[FOR_FIRST_PREHEADER]] ], [ [[TMP15:%.*]], %[[FOR_FIRST_LATCH:.*]] ]
; CHECK-NEXT:    [[INDVARS_IV23:%.*]] = phi i64 [ 0, %[[FOR_FIRST_PREHEADER]] ], [ [[INDVARS_IV_NEXT3:%.*]], %[[FOR_FIRST_LATCH]] ]
; CHECK-NEXT:    [[TMP:%.*]] = add nsw i32 [[DOT014]], -3
; CHECK-NEXT:    [[TMP8:%.*]] = add nuw nsw i64 [[INDVARS_IV23]], 3
; CHECK-NEXT:    [[TMP9:%.*]] = trunc i64 [[TMP8]] to i32
; CHECK-NEXT:    [[TMP10:%.*]] = mul nsw i32 [[TMP]], [[TMP9]]
; CHECK-NEXT:    [[TMP11:%.*]] = trunc i64 [[INDVARS_IV23]] to i32
; CHECK-NEXT:    [[TMP12:%.*]] = srem i32 [[TMP10]], [[TMP11]]
; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[ARG]], i64 [[INDVARS_IV23]]
; CHECK-NEXT:    store i32 [[TMP12]], ptr [[TMP13]], align 4
; CHECK-NEXT:    br label %[[FOR_FIRST_LATCH]]
; CHECK:       [[FOR_FIRST_LATCH]]:
; CHECK-NEXT:    [[INDVARS_IV_NEXT3]] = add nuw nsw i64 [[INDVARS_IV23]], 1
; CHECK-NEXT:    [[TMP15]] = add nuw nsw i32 [[DOT014]], 1
; CHECK-NEXT:    [[EXITCOND4:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT3]], 100
; CHECK-NEXT:    br i1 [[EXITCOND4]], label %[[FOR_FIRST]], label %[[FOR_FIRST_EXIT:.*]]
; CHECK:       [[FOR_FIRST_EXIT]]:
; CHECK-NEXT:    br label %[[FOR_NEXT:.*]]
; CHECK:       [[FOR_NEXT]]:
; CHECK-NEXT:    br label %[[FOR_SECOND_PREHEADER:.*]]
; CHECK:       [[FOR_SECOND_PREHEADER]]:
; CHECK-NEXT:    br label %[[FOR_SECOND:.*]]
; CHECK:       [[FOR_SECOND]]:
; CHECK-NEXT:    [[DOT02:%.*]] = phi i32 [ 0, %[[FOR_SECOND_PREHEADER]] ], [ [[TMP28:%.*]], %[[FOR_SECOND_LATCH:.*]] ]
; CHECK-NEXT:    [[INDVARS_IV1:%.*]] = phi i64 [ 3, %[[FOR_SECOND_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_SECOND_LATCH]] ]
; CHECK-NEXT:    [[TMP20:%.*]] = add nsw i32 [[DOT02]], -3
; CHECK-NEXT:    [[TMP21:%.*]] = add nuw nsw i64 [[INDVARS_IV1]], 3
; CHECK-NEXT:    [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
; CHECK-NEXT:    [[TMP23:%.*]] = mul nsw i32 [[TMP20]], [[TMP22]]
; CHECK-NEXT:    [[TMP24:%.*]] = trunc i64 [[INDVARS_IV1]] to i32
; CHECK-NEXT:    [[TMP25:%.*]] = srem i32 [[TMP23]], [[TMP24]]
; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [1024 x i32], ptr @B, i64 0, i64 [[INDVARS_IV1]]
; CHECK-NEXT:    store i32 [[TMP25]], ptr [[TMP26]], align 4
; CHECK-NEXT:    br label %[[FOR_SECOND_LATCH]]
; CHECK:       [[FOR_SECOND_LATCH]]:
; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV1]], 1
; CHECK-NEXT:    [[TMP28]] = add nuw nsw i32 [[DOT02]], 1
; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], 100
; CHECK-NEXT:    br i1 [[EXITCOND]], label %[[FOR_SECOND]], label %[[FOR_END:.*]]
; CHECK:       [[FOR_END]]:
; CHECK-NEXT:    ret void
;
for.first.preheader:
  br label %for.first

for.first:                                       ; preds = %for.first.preheader, %for.first.latch
  %.014 = phi i32 [ 0, %for.first.preheader ], [ %tmp15, %for.first.latch ]
  %indvars.iv23 = phi i64 [ 0, %for.first.preheader ], [ %indvars.iv.next3, %for.first.latch ]
  %tmp = add nsw i32 %.014, -3
  %tmp8 = add nuw nsw i64 %indvars.iv23, 3
  %tmp9 = trunc i64 %tmp8 to i32
  %tmp10 = mul nsw i32 %tmp, %tmp9
  %tmp11 = trunc i64 %indvars.iv23 to i32
  %tmp12 = srem i32 %tmp10, %tmp11
  %tmp13 = getelementptr inbounds i32, ptr %arg, i64 %indvars.iv23
  store i32 %tmp12, ptr %tmp13, align 4
  br label %for.first.latch

for.first.latch:                                 ; preds = %for.first
  %indvars.iv.next3 = add nuw nsw i64 %indvars.iv23, 1
  %tmp15 = add nuw nsw i32 %.014, 1
  %exitcond4 = icmp ne i64 %indvars.iv.next3, 100
  br i1 %exitcond4, label %for.first, label %for.first.exit

for.first.exit:                                  ; preds: %for.first.latch
  br label %for.next

for.next:                                        ; preds = %for.first.exit
  br label %for.second.preheader

for.second.preheader:                            ; preds = %for.next
  br label %for.second

for.second:                                      ; preds = %for.second.preheader, %for.second.latch
  %.02 = phi i32 [ 0, %for.second.preheader ], [ %tmp28, %for.second.latch ]
  %indvars.iv1 = phi i64 [ 3, %for.second.preheader ], [ %indvars.iv.next, %for.second.latch ]
  %tmp20 = add nsw i32 %.02, -3
  %tmp21 = add nuw nsw i64 %indvars.iv1, 3
  %tmp22 = trunc i64 %tmp21 to i32
  %tmp23 = mul nsw i32 %tmp20, %tmp22
  %tmp24 = trunc i64 %indvars.iv1 to i32
  %tmp25 = srem i32 %tmp23, %tmp24
  %tmp26 = getelementptr inbounds [1024 x i32], ptr @B, i64 0, i64 %indvars.iv1
  store i32 %tmp25, ptr %tmp26, align 4
  br label %for.second.latch

for.second.latch:                                ; preds = %for.second
  %indvars.iv.next = add nuw nsw i64 %indvars.iv1, 1
  %tmp28 = add nuw nsw i32 %.02, 1
  %exitcond = icmp ne i64 %indvars.iv.next, 100
  br i1 %exitcond, label %for.second, label %for.end

for.end:                                         ; preds = %for.second.latch
  ret void
}