| # RUN: llc -o - %s -mtriple=s390x-linux-gnu -mcpu=z16 -verify-machineinstrs \ |
| # RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler 2>&1\ |
| # RUN: | FileCheck %s |
| # REQUIRES: asserts |
| |
| # Some tests for Pressure Diffs of scheduling units. Each interesting register |
| # class is used in a def-use sequence and the initial Pressure Diff of each SU |
| # is checked. For all GPRs the GRX32Bit PressureSet should be present, and for |
| # all FP/Vector regs the VR16Bit PressureSet should be affected. |
| |
| --- | |
| |
| define void @fun0() { ret void } |
| ... |
| |
| |
| # GR64Bit => GRX32Bit 2 |
| # |
| # CHECK: ********** MI Scheduling ********** |
| # CHECK-NEXT: fun0:%bb.0 |
| # CHECK: SU(0): %0:gr64bit = LGHI 0 |
| # CHECK: Pressure Diff : GRX32Bit -2 |
| # CHECK: SU(1): STG %0:gr64bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit 2 |
| # CHECK: SU(2): %1:grx32bit = LHIMux 0 |
| # CHECK: Pressure Diff : GRX32Bit -1 |
| # CHECK: SU(3): STMux %1:grx32bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit 1 |
| # CHECK: SU(4): %2:gr32bit = LHI 0 |
| # CHECK: Pressure Diff : GR32Bit -1 GRX32Bit -1 |
| # CHECK: SU(5): ST %2:gr32bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GR32Bit 1 GRX32Bit 1 |
| # CHECK: SU(6): %3:grh32bit = IIHF 0 |
| # CHECK: Pressure Diff : GRH32Bit -1 GRX32Bit -1 |
| # CHECK: SU(7): STFH %3:grh32bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRH32Bit 1 GRX32Bit 1 |
| # CHECK: SU(8): %4:addr64bit = LGHI 0 |
| # CHECK: Pressure Diff : GRX32Bit -2 |
| # CHECK: SU(9): STG %4:addr64bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit 2 |
| # CHECK: SU(10): %5:addr32bit = LHI 0 |
| # CHECK: Pressure Diff : GR32Bit -1 GRX32Bit -1 |
| # CHECK: SU(11): ST %5:addr32bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GR32Bit 1 GRX32Bit 1 |
| # CHECK: SU(12): %6:gr128bit = L128 $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit -4 |
| # CHECK: SU(13): ST128 %6:gr128bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit 4 |
| # CHECK: SU(14): %7:addr128bit = L128 $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit -4 |
| # CHECK: SU(15): ST128 %7:addr128bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : GRX32Bit 4 |
| # CHECK: SU(16): %8:vr16bit = LEFR_16 undef %9:gr32bit |
| # CHECK: Pressure Diff : VR16Bit -1 |
| # CHECK: SU(17): dead %9:gr32bit = LFER_16 %8:vr16bit |
| # CHECK: Pressure Diff : VR16Bit 1 |
| # CHECK: SU(18): %10:vr32bit = LEFR undef %11:gr32bit |
| # CHECK: Pressure Diff : VR16Bit -1 |
| # CHECK: SU(19): dead %12:gr64bit = LFER %10:vr32bit |
| # CHECK: Pressure Diff : VR16Bit 1 |
| # CHECK: SU(20): %13:vr64bit = SelectVR64 undef %14:vr64bit, undef %15:vr64bit |
| # CHECK: Pressure Diff : VR16Bit -1 |
| # CHECK: SU(21): VST64 %13:vr64bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : VR16Bit 1 |
| # CHECK: SU(22): %16:vr128bit = VZERO |
| # CHECK: Pressure Diff : VR16Bit -1 |
| # CHECK: SU(23): VST %16:vr128bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : VR16Bit 1 |
| # CHECK: SU(24): %17:fp16bit = LZER_16 |
| # CHECK: Pressure Diff : FP16Bit -1 VR16Bit -1 |
| # CHECK: SU(25): STE16 %17:fp16bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit 1 VR16Bit 1 |
| # CHECK: SU(26): %18:fp32bit = LZER |
| # CHECK: Pressure Diff : FP16Bit -1 VR16Bit -1 |
| # CHECK: SU(27): STE %18:fp32bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit 1 VR16Bit 1 |
| # CHECK: SU(28): %19:fp64bit = LZDR |
| # CHECK: Pressure Diff : FP16Bit -1 VR16Bit -1 |
| # CHECK: SU(29): STD %19:fp64bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit 1 VR16Bit 1 |
| # CHECK: SU(30): %20:vf128bit = VL $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit -1 VR16Bit -1 |
| # CHECK: SU(31): VST %20:vf128bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit 1 VR16Bit 1 |
| # CHECK: SU(32): %21:fp128bit = LZXR |
| # CHECK: Pressure Diff : FP16Bit -2 VR16Bit -2 |
| # CHECK: SU(33): STX %21:fp128bit, $noreg, 0, $noreg |
| # CHECK: Pressure Diff : FP16Bit 2 VR16Bit 2 |
| --- |
| name: fun0 |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| |
| %0:gr64bit = LGHI 0 |
| STG %0, $noreg, 0, $noreg |
| |
| %1:grx32bit = LHIMux 0 |
| STMux %1, $noreg, 0, $noreg |
| |
| %2:gr32bit = LHI 0 |
| ST %2, $noreg, 0, $noreg |
| |
| %3:grh32bit = IIHF 0 |
| STFH %3, $noreg, 0, $noreg |
| |
| %4:addr64bit = LGHI 0 |
| STG %4, $noreg, 0, $noreg |
| |
| %5:addr32bit = LHI 0 |
| ST %5, $noreg, 0, $noreg |
| |
| %6:gr128bit = L128 $noreg, 0, $noreg |
| ST128 %6, $noreg, 0, $noreg |
| |
| %7:addr128bit = L128 $noreg, 0, $noreg |
| ST128 %7, $noreg, 0, $noreg |
| |
| %8:vr16bit = LEFR_16 undef %9:gr32bit |
| %9:gr32bit = LFER_16 %8 |
| |
| %11:vr32bit = LEFR undef %10:gr32bit |
| %12:gr64bit = LFER %11 |
| |
| %13:vr64bit = SelectVR64 undef %14:vr64bit, undef %15:vr64bit, 0, 0, implicit undef $cc |
| VST64 %13, $noreg, 0, $noreg |
| |
| %16:vr128bit = VZERO |
| VST %16, $noreg, 0, $noreg |
| |
| %17:fp16bit = LZER_16 |
| STE16 %17, $noreg, 0, $noreg |
| |
| %18:fp32bit = LZER |
| STE %18, $noreg, 0, $noreg |
| |
| %19:fp64bit = LZDR |
| STD %19, $noreg, 0, $noreg |
| |
| %20:vf128bit = VL $noreg, 0, $noreg |
| VST %20, $noreg, 0, $noreg |
| |
| %21:fp128bit = LZXR |
| STX %21, $noreg, 0, $noreg |
| |
| NOP $noreg, 0, $noreg ; enable reg pressure tracking (>36 instrs). |
| NOP $noreg, 0, $noreg |
| NOP $noreg, 0, $noreg |
| NOP $noreg, 0, $noreg |
| |
| Return |
| ... |
